DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
The amendment filed on 04/27/2026 has been accepted and entered. Claims 1-2, 7-25, 27-28 remain pending in this application. Applicant’s amendments to the Specification, Drawing, and Claims have overcome each and every objection, 112(b) rejection and 35 USC § 101 rejection previously set forth in the Non-Final Office Action mailed 03/25/2026.
Election/Restrictions
Claims 17-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-9, 11-13, 27-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS.
Regarding claim 1, NPLHuang13 discloses a high-electron-mobility transistor structure (Abstract Lines L1-3), comprising:
an epitaxial structure(AlN/GaN grown by MOCVD so epitaxial structure-pp3019 [Introduction] Column C2 L22-23, Fig 1(b)), comprising
a heterojunction (GaN/AlN/GaN junction-Abstract L2) consisting of
a first semiconductor layer (first layer GaN-Abstract L2) and
a second semiconductor layer(second layer AlN-Abstract L2),
a carrier channel being formed between the first semiconductor layer and the second semiconductor layer(AlN barrier maximizing 2DEG density so carrier channel, and allowing good control over channel carrier so the carrier channel is just under the layer AlN, consequently is between the first layer and the second layer-pp3019 [Introduction] C1L15-C2L1); and
a source electrode (Fig 2(i)),
a drain electrode (Fig 2(i)), and
a gate electrode, disposed on the epitaxial structure (Gate electrode on epitaxial growth AlN/GaN Fig 2(i), Fig 1(b)),
the source electrode being electrically connected with the drain electrode through the carrier channel (Source electrode and Drain electrode are part of an equivalent circuit and are connected through the carrier channel-Fig 1(b));
wherein, a coincidence rate between an orthographic projection of the-a gate foot of the gate electrode on the first semiconductor layer and an orthographic projection of the second semiconductor layer on the first semiconductor layer is more than 80% (SiO2 is 500 nm-thick covered by a 50nm-thick SiNx layer so the total thickness is 600nm-C1 L21, Fig 2(b); after etching the AlN/GaN is also 600nm-thick being aligned with the SiO2/ SiNx-Fig 2(c); SiO2 is removed followed by Al2O3 deposition of 6nm so the recess is 488 nm-thick (500-12=488nm)-C2 L22-23, Fig 2(h); deposition of gate electrode in recess so gate electrode foot is 488nm wide-Fig 2(i); the orthographic projection of the gate foot so projection vertically on the first semiconductor GaN, is its width; The orthographic projection of the second semiconductor layer AlN is also it width, so the ratio between the width of the AlN/GaN layers and the gate-electrode-foot width is then 488nm/600nm=81%, so larger than 80%-Examiner's annotated Fig 2).
wherein the epitaxial structure further comprises
a heavily doped region (heavily doped region n+ Gan-Fig 1 (b)) and
a high resistance region (High resistance region high-k SiNx/Al2O3-Fig1(b), Fig 2(i), p3020 [III] C2 L 21-22;
the heavily doped region is arranged on the heterojunction (High resistance region high-k SiNx/Al2O3 arranged on heterojunction GaN/AlN/GaN junction -Fig1(b), Fig 2(i)) and
forms an ohmic contact with the carrier channel (a heavily doped region n+ GaN region of epitaxial structure in contact with carrier channel GaN having resistances Rs and Rd so forming ohmic contact-Fig 1(b)),
the source electrode and the drain electrode form an ohmic contact with the heavily doped region (a heavily doped region n+ GaN region of epitaxial structure in contact with carrier channel GaN having resistances Rs and Rd so forming ohmic contact-Fig 1(b)),
the high resistance region is disposed on the heavily doped region (Ti-based alloy being chosen as the ohmic contact metal for n+ GaN layer, so source/drain electrodes being in ohmic contact with the heavily doped region n+ GaN-p3020 [III] C2 L 31-32),
the source electrode is isolated from the gate electrode by the high resistance region (The high resistance SiNx/Al2O3 is between Source and gate electrode, so isolating one from the other-Examiner's annotated Fig 2 (i), Fig 1(b)), and
the drain electrode is isolated from the gate electrode by the high resistance region (the high resistance SiNx/Al2O3 is between Drain and gate electrode, so isolating one from the other-Examiner's annotated Fig 2 (i), Fig 1(b)); and
wherein the heavily doped region comprises
a first heavily doped region matched with the source electrode (first heavily doped region Left n+ GaN matched with the source electrode S- Examiner's annotated Fig 2(i)) and
a second heavily doped region matched with the drain electrode (second heavily doped region Right n+ GaN matched with the Drain electrode D- Examiner's annotated Fig 2(i)),
the first heavily doped region and the second heavily doped region are respectively located at two sides of the second semiconductor layer (first heavily doped region Left n+ GaN and second heavily doped region Right n+ GaN located on each side of the second semiconductor layer Gan of the Heterostructure AlN/GaN- Examiner's annotated Fig 2(i)),
the high resistance region comprises
a first high resistance region matched with the source electrode (first high resistance region Left SiNx/Al2O3 matched with the source electrode S- Examiner's annotated Fig 2(i)) and
a second high resistance region matched with the drain electrode (second high resistance region Right SiNx/Al2O3 matched with the Drain electrode D- Examiner's annotated Fig 2(i)), and
wherein the source electrode penetrates through the first high resistance region (Source electrode S penetrating first high resistance region Left SiNx/Al2O3-Frig 1(b), Fig 2(i)) and
is in an ohmic contact with the first heavily doped region (Ti-based alloy being chosen as the ohmic contact metal for n+ GaN layer, so source/drain electrodes S and D being in ohmic contact with the first heavily doped region Left n+ GaN Fig 1(b), Fig 2(i), p3020 [III] C2 L 31-32), and
the drain electrode penetrates through the second high resistance region (Drain electrode D penetrating second high resistance region Right SiNx/Al2O3-Frig 1(b), Fig 2(i)) and
is in an ohmic contact with the second heavily doped region (Ti-based alloy being chosen as the ohmic contact metal for n+ GaN layer, so source/drain electrodes S and D being in ohmic contact with the second heavily doped region Right n+ GaN Fig 1(b), Fig 2(i), p3020 [III] C2 L 31-32).
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Regarding claim 2, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the orthographic projection of the gate foot on the first semiconductor layer coincides with the orthographic projection of the second semiconductor layer on the first semiconductor layer (dashed line rectangle shows the orthographic projection of the gate foot on the first semiconductor layer GaN; the second semiconductor layer AlN is aligned with the First semiconductor layer GaN so its orthographic projection is the top surface of the first semiconductor layer GaN; the orthographic projection of the gate foot on the first semiconductor layer coincides with the orthographic projection of the second semiconductor layer on the first semiconductor layer-Examiner's annotated Fig 2 with a focus on Fig 2(i)); and,
the carrier channel is distributed in a region covered by the orthographic projection of the gate foot electrode on the epitaxial structure (GaN carrier channel being in a region covered by orthographic projection shown by the dashed line rectangle-Examiner's annotated Fig 2).
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Regarding claim 7, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein an upper surface of the heavily doped region is higher than a surface of the carrier channel (upper surface of the heavily doped region n+ GaN is higher than a surface of the carrier channel GaN-Examiner's annotated Fig 2(i)).
Regarding claim 8, NPLHuang13 discloses all the elements of claim 7, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the carrier channel is a two-dimensional electron gas channel (Carrier Channel GaN capped by barrier AlN lead to maximize 2D electron gas so the carrier channel is a two-dimensional electron gas channel-pp 3019 [Introduction] C1 L15-19),
the second semiconductor layer is arranged on the first semiconductor layer (Second semiconductor layer AlN arranged on First semiconductor layer GaN-Examiner's annotated Fig 2) , and
the first and second heavily doped regions are of n type (the first and second heavily doped regions L/R n+ GaN so n type-Examiner's annotated Fig 2); or
the carrier channel is a two-dimensional hole gas channel, and the first and second heavily doped regions are of p type.
Regarding claim 9, NPLHuang13 discloses all the elements of claim 8, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the first semiconductor layer comprises
a first region and a second region (GaN comprising a first and second regions-Examiner's annotated Fig 2(i)),
a bulge portion is formed in the first region (Examiner's annotated Fig 2(i)),
the second semiconductor layer is arranged on the bulge portion (the second semiconductor layer AlN arranged on the bulge portion-Examiner's annotated Fig 2(i)),
the first heavily doped region and the second heavily doped region are arranged on the second region (first heavily doped region and second heavily doped region L/R n+ GaN arranged on the second region-Examiner's annotated Fig 2(i)) and
distributed at two sides of the bulge portion (first heavily doped region and second heavily doped region L/R n+ GaN arranged on each side of the bulge-Examiner's annotated Fig 2(i).
Regarding claim 12, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the gate electrode comprises a gate cap and a gate foot (Fig 1(b)),
wherein the gate cap is arranged on the high resistance region and supported by the high resistance region (Gate cap on high resistance region SiNx-Examiner's annotated Fig 2(i)),
the gate foot is arranged in the epitaxial structure (gate foot between the n+ GaN L/R regions grown by MOCVD so in the epitaxial structure-Examiner's annotated Fig 2(i), pp3019 [Introduction] Column C2 L22-23), and
the carrier channel is distributed right under the gate foot (Carrier channel GaN right under the gate foot-Examiner's annotated Fig 2(i));
a size of the gate cap in a direction of a source-drain channel is larger than that a size of the gate foot in the direction of the source-drain channel (the gate electrode is T-shaped so the width of the cap is larger than the width of the foot in the horizontal direction which has been interpretated as the source-drain channel direction-Fig 2(i)), and
the size of the gate foot in the direction of the source-drain channel is smaller than or equal to a length of the carrier channel (Width of the gate foot is smaller than or equal to the length of the carrier channel GaN in the horizontal direction-Examiner's annotated Fig 2(i));
the gate electrode is a T-type gate (the gate electrode is T-shaped-Examiner's annotated Fig 2(i)); and
the gate electrode is electrically isolated from the second semiconductor layer by the dielectric layer (gate electrode is electrically isolated from second semiconductor AlN by dielectric layer Al2O3-Fig 1); and
a side wall dielectric layer is also formed between the side wall of the gate foot and the high resistance region (side wall dielectric layer Al2O3 formed on the vertical side wall of gate foot and high resistance SiNx-Fig 1).
Regarding claim 13, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein a dielectric layer is arranged between the gate electrode and the heterojunction (dielectric layer Al2O3 between gate electrode and heterojunction Cap layer GaN/2nd semiconductor AlN/1st semiconductor GaN-Fig 1);
the dielectric layer is further configured for obstructing the gate electrode and the high resistance region (dielectric layer Al2O3 vertically between gate electrode and high resistance region SiNx so obstructing them-Fig 1), or
the gate electrode is directly isolated from the high resistance region by air; and
the dielectric layer further extends and covers a surface of the epitaxial structure (dielectric layer Al2O3 horizontally between gate electrode and high resistance region SiNx so extending and covering the epitaxial structure-Fig 1), and
the source electrode and the drain electrode are matched with the epitaxial structure through corresponding windows formed on the dielectric layer(Source electrode S and Drain electrode D matched through opening to the epitaxial structure-Fig 1).
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Regarding claim 27, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a power amplifier, comprising
the high-electron-mobility transistor structure according to claim 1 (GaN high-electron mobility transistors (HEMTs) practical advantages in applications of RF/millimeter-wave power amplifier and power switching so power amplifier comprising HEMT-pp3019 [Introduction] C1 L 1-4).
Regarding claim 28, NPLHuang13 discloses all the elements of claim 27, as noted above.
NPLHuang13 further discloses a power amplifier comprising
a power amplifier with a radio frequency wave band, a millimeter wave band or a terahertz wave band (GaN high-electron mobility transistors (HEMTs) practical advantages in applications of RF/millimeter-wave power amplifier and power switching so power amplifier with radio frequency wave band-pp3019 [Introduction] C1 L 1-4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS in view of Moon et al (US-20210013307-A1-Moon07).
Regarding claim 10, NPLHuang13 discloses all the elements of claim 7, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein a cap layer is distributed between the gate electrode and the second semiconductor layer (Cap layer GaN on second conductor layer AlN-Examiner's annotated Fig 2(i)).
the gate electrode is electrically isolated from the cap layer by the dielectric layer (Gate electrode electrically isolated from cap layer GaN by dielectric layer Al2O3 (Fig 1).
NPLHuang13 does not disclose a high-electron-mobility transistor structure
Wherein the epitaxial structure further comprises an insertion layer distributed between the first semiconductor layer and the second semiconductor layer.
Moon07 teaches a high-electron-mobility transistor structure
Wherein the epitaxial structure further comprises an insertion layer distributed between the first semiconductor layer and the second semiconductor layer (insertion layer AlGaN 18 distributed between first semiconductor layer GaN 16 and second semiconductor layer AiN 22-Fig 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the high-electron-mobility transistor structure of NPLHuang13, as taught by Moon07 for the purpose of mitigating the reduced breakdown voltage of an AlN/GaN device (Moon07: [0056]).
Regarding claim 11, NPLHuang13 and Moon07 combination teaches all the elements of claim 10, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the epitaxial structure comprises a Ga polar surface (pp3019 [Introduction] C2 L3-4) or
an N polar surface (pp3019 [Introduction] C2 L3-4).
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Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS in view of Grote et al. (US 20220376060 A1-Grote60).
Regarding claim 15, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 does not disclose a high-electron-mobility transistor structure further comprising
an isolation region formed in the epitaxial structure and
configured for isolating an active region.
Grote60 teaches a high-electron-mobility transistor structure further comprising
an isolation region formed in the epitaxial structure (isolation region 120 formed in the semiconductor substrate 110 to define an active zone 125; implantation procedure on epitaxial layers create 122 from 120, so isolation region formed in the epitaxial structure-[0021] L1-9) and
configured for isolating an active region (isolation region 120 formed in the semiconductor substrate 110 to define an active zone 125-[0021] L1-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the high-electron-mobility transistor structure of NPLHuang13, as taught byGrove60 for the purpose of creating a 2-DEGby disposing the channel layer over the barrier layer (Grove60: [0020] L27-30).
Regarding claim 16, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein a material of the epitaxial structure comprises III-V group compounds (epitaxial layer AlN/GaN so III-V group-Fig 1);
the high-electron-mobility transistor structure comprises a nitrogen polar high-electron-mobility transistor (HEMT) device structure (pp3019 [Introduction] C2 L3-4) or
an HEMT device structure having a back barrier structure;
the high-electron-mobility transistor structure is of a depletion-mode device structure or
an enhanced device structure (pp3019 [Design of Gate-last Device] C2 L 1-2);
the high-electron-mobility transistor structure further comprises
a substrate where the epitaxial structure is formed (Si Substrate with epitaxial structure GaN/AlN/GaN-Fig 1).
PLHuang13 does not disclose a high-electron-mobility transistor structure
Wherein the epitaxial structure further comprises
a buffer layer distributed between the substrate and the first semiconductor layer.
Grote60 teaches a high-electron-mobility transistor structure
wherein the epitaxial structure further comprises
a buffer layer distributed between the substrate and the first semiconductor layer (buffer layer 104 between substrate 102 and first semiconductor layer 107-Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the high-electron-mobility transistor structure of NPLHuang13, as taught byGrove60 for the purpose of creating a 2-DEGby disposing the channel layer over the barrier layer (Grote60: [0020] L27-30).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, the prior art of record does not teach or suggest a high-electron-mobility transistor structure, namely “wherein an interface between the heavily doped region and the high resistance region is regulated by mutant doping or gradual doping”.
Reference such as Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS, teaches [preamble], but does not teach or suggest a high-electron-mobility transistor structure , namely “wherein an interface between the heavily doped region and the high resistance region is regulated by mutant doping or gradual doping”, in combination with other claimed elements.
Response to Arguments
Applicant’s arguments see pages 12-33 of Remarks, filed on 04/27/2026 with respect to claim(s) 1 have been fully considered but they are not persuasive.
Applicant’s argument states that Huang in combination with Grote fails to teach the claimed structural limitation “wherein the epitaxial structure further comprises a heavily doped region and a high resistance region ... the high resistance region is disposed on the heavily doped region”, the argument is not persuasive because the references combination does not teach a stacked arrangement. The limitation “disposed on” does not mean vertically stacked per se.
Additionally, applicant’s argument states that Huang fails to teach the claimed structural and electrical relationship that "the heavily doped region is arranged on the heterojunction and forms an ohmic contact with the carrier channel, [and] the source electrode and the drain electrode form an ohmic contact with the heavily doped region”, the argument is not persuasive because the limitation does not mean that doped regions have to be beneath high resistance regions.
Finally, applicant’s argument states that Huang entirely fails to teach the most important limitation of claim 1, namely, "wherein the source electrode penetrates through the first high resistance region and is in an ohmic contact with the first heavily doped region, and the drain electrode penetrates through the second high resistance region and is in an ohmic contact with the second heavily doped region”, the argument is not persuasive because “penetrate through” means that the high resistance region is etched from top to bottom through the whole thickness of the high resistance region, to open a space to form the source and drain electrode( Fig 2(g) , Fig 2(h)).
The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claim 1 has been amended to further define the claimed subject matter see pages 2-10 of Amendments to Claims, filed on 3/25/2026.
Claim(s) 1-2, 7-9, 12-13, 27-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS, as described above
Therefore, claim(s) 1-2, 7-9, 11-13, 27-28 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS in view of Moon et al (US-20210013307-A1-Moon07), as described above.
Therefore, claim(s) 10-11 stand rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS in view of Moon et al (US-20210013307-A1-Moon07).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS in view of Grote et al. (US 20220376060 A1-Grote60), as described above.
Therefore, claim(s) 15-16 stand rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS in view of Grote et al. (US 20220376060 A1-Grote60).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 06/01/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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