DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 17-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim.
Applicant's election with traverse of Claims 1-16 and 26-28 drawn to a high-electron-mobility transistor structure, in the reply filed on 01/28/2026 is acknowledged. The traversal is on the ground(s) that there is Unity of invention, as the prior art cited does not show the common technical feature “wherein, a coincidence rate between an orthographic projection of a gate foot of the gate electrode on the first semiconductor layer and an orthographic projection of the second semiconductor layer on the first semiconductor layer is more than 80%”.
This is not found persuasive because this technical feature is not a special technical feature as it does not make a contribution over the prior art in view of Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS
A high-electron-mobility transistor structure (Abstract Lines L1-3)
wherein, a coincidence rate between an orthographic projection of the-a gate foot of the gate electrode on the first semiconductor layer and an orthographic projection of the second semiconductor layer on the first semiconductor layer is more than 80% (SiO2 is 500 nm-thick covered by a 50nm-thick SiNx layer so the total thickness is 600nm-C1 L21, Fig 2(b); after etching the AlN/GaN is also 600nm-thick being aligned with the SiO2/ SiNx-Fig 2(c); SiO2 is removed followed by Al2O3 deposition of 6nm so the recess is 488 nm-thick (500-12=488nm)-C2 L22-23, Fig 2(h); deposition of gate electrode in recess so gate electrode foot is 488nm wide-Fig 2(i); the orthographic projection of the gate foot so projection vertically on the first semiconductor GaN, is its width; The orthographic projection of the second semiconductor layer AlN is also it width, so the ratio between the width of the AlN/GaN layers and the gate-electrode-foot width is then 488nm/600nm=81%, so larger than 80%-Examiner's annotated Fig 2).
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The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “ohmic contact layer” of claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “at least partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region " of claim 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 3-15 is/are objected to because of the following informalities:
Claim 3 recites “ohmic contact” in line L4, but should read –an ohmic contact--.
Claim 4 recites “distributed” in line L2, but should read –etched--.
Claim 7 recites “then is” in lines L11, but should read –then are--.
Claim 14 recites “mutant doping or gradual doping" in Line L 5, but should read – a mutant doping or a gradual doping--.
The balance of claims are objected to for being dependent upon an already objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-16 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the limitation "the orthographic projection of the gate electrode" in Line L4, renders the claim indefinite because the antecedent basis is unclear as to whether “the orthographic projection of the gate electrode" (Line L4) refers to a new orthographic projection of the gate electrode or the "the orthographic projection of the gate foot electrode" previously cited in Line L8 of claim 1. In the purpose of compact prosecution, "the orthographic projection of the gate electrode" has been interpretated as the orthographic projection of the gate foot electrode.
Regarding claim 2, the limitation "and/or" in Line 4, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 2 results in the following options:
Option 1: wherein the orthographic projection of the gate foot on the first semiconductor layer coincides with the orthographic projection of the second semiconductor layer on the first semiconductor layer; and the carrier channel is distributed in a region covered by the orthographic projection of the gate electrode on the epitaxial structure.
Option 2: wherein the orthographic projection of the gate foot on the first semiconductor layer coincides with the orthographic projection of the second semiconductor layer on the first semiconductor layer.
Option 3: wherein the carrier channel is distributed in a region covered by the orthographic projection of the gate electrode on the epitaxial structure.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein the orthographic projection of the gate foot on the first semiconductor layer coincides with the orthographic projection of the second semiconductor layer on the first semiconductor layer.— in Option 2.
Regarding claim 3, the limitation "ohmic contact" in Line L6, renders the claim indefinite because the antecedent basis is unclear as to whether “ohmic contact" (Line L6) refers to a new ohmic contact or the "ohmic contact" previously cited in Line L4 of claim 3. In the purpose of compact prosecution, "ohmic contact" has been interpretated as an ohmic contact.
Regarding claim 4, the limitation "and/or" in Line 5, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 4 results in the following options:
Option 1: wherein a groove is distributed in a region of the ohmic contact corresponding to the gate electrode, at least a bottom of the gate foot and the second semiconductor layer are arranged in the groove; and the gate electrode is electrically isolated from the ohmic contact layer by a dielectric layer, or the gate electrode is isolated from the ohmic contact layer by air.
Option 2: wherein a groove is distributed in a region of the ohmic contact corresponding to the gate electrode, at least a bottom of the gate foot and the second semiconductor layer are arranged in the groove.
Option 3: wherein the gate electrode is electrically isolated from the ohmic contact layer by a dielectric layer, or the gate electrode is isolated from the ohmic contact layer by air
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein a groove is distributed in a region of the ohmic contact corresponding to the gate electrode, at least a bottom of the gate foot and the second semiconductor layer are arranged in the groove—in Option 2.
Regarding claim 5, the limitation "and/or" in Line 4, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 5 results in the following options:
Option 1: wherein an included angle of 60-90° is formed between a side wall of the groove and a surface of the first semiconductor layer; and a gate cap of the gate electrode covers the dielectric layer on the groove.
Option 2: wherein an included angle of 60-90° is formed between a side wall of the groove and a surface of the first semiconductor layer.
Option 3: wherein a gate cap of the gate electrode covers the dielectric layer on the groove.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein an included angle of 60-90° is formed between a side wall of the groove and a surface of the first semiconductor layer –in Option 2.
Regarding claim 6, the limitation "ohmic contact" in Line L3, renders the claim indefinite because the antecedent basis is unclear as to whether “ohmic contact" (Line L3) refers to a new ohmic contact or the "ohmic contact" previously cited in Line L4 of claim 3. In the purpose of compact prosecution, "ohmic contact" has been interpretated as an ohmic contact.
Regarding claim 6, the limitation "ohmic contact" in Line L4, renders the claim indefinite because the antecedent basis is unclear as to whether “ohmic contact" (Line L4) refers to a new ohmic contact or the "ohmic contact" previously cited in Line L4 of claim 3. In the purpose of compact prosecution, "ohmic contact" has been interpretated as an ohmic contact.
Regarding claim 6, the limitation "the gate" in Line L7, renders the claim indefinite because the antecedent basis is unclear as to whether “the" (Line L7) refers to a new gate or the "gate electrode" previously cited in Line L5 of claim 1. In the purpose of compact prosecution, "the gate" has been interpretated as the gate electrode.
Regarding claim 6, the limitation " the heavily doped ohmic contact layer" in Lines L7-8, renders the claim indefinite because the antecedent basis is unclear as to whether “the heavily doped ohmic contact layer " (Lines L7-8) refers to a new heavily doped ohmic contact layer or the "the heavily doped region" previously cited in Line L2 of claim 6, or “the ohmic contact layer” previously cited in Line L2 of claim 3. In the purpose of compact prosecution, "the heavily doped ohmic contact layer" has been interpretated as the heavily doped region.
Regarding claim 7, the limitation " at least partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region" in Lines L9-11, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear how a partial region can penetrate itself and there is no structure shown on the drawings that can illustrate how the partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region. In the purpose of compact prosecution, " at least partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region" has been interpretated as at least partial regions of the first high resistance region and the second high resistance region are in the first high resistance region and the second high resistance region.
Regarding claim 7, the limitation "and/or" in Line 4, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 7 results in the following options:
Option 1: wherein an upper surface of the heavily doped region is higher than a surface of the carrier channel; and the heavily doped region comprises a first heavily doped region matched with the source electrode and a second heavily doped region matched with the drain electrode, the first heavily doped region and the second heavily doped region are respectively located at two sides of the second semiconductor layer, the high resistance region comprises a first high resistance region matched with the source electrode and a second high resistance region matched with the drain electrode, and at least partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region and is in ohmic contact with the first heavily doped region and the second heavily doped region.
Option 2: wherein an upper surface of the heavily doped region is higher than a surface of the carrier channel.
Option 3: wherein the heavily doped region comprises a first heavily doped region matched with the source electrode and a second heavily doped region matched with the drain electrode, the first heavily doped region and the second heavily doped region are respectively located at two sides of the second semiconductor layer, the high resistance region comprises a first high resistance region matched with the source electrode and a second high resistance region matched with the drain electrode, and at least partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region and is in ohmic contact with the first heavily doped region and the second heavily doped region.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein an upper surface of the heavily doped region is higher than a surface of the carrier channel—in Option 2.
Regarding claim 10, the limitation "and/or" in Line 6, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 10 results in the following options:
Option 1: wherein a cap layer is distributed between the gate electrode and the second semiconductor layer; the gate electrode is electrically isolated from the cap layer by the dielectric layer; and the epitaxial structure further comprises an insertion layer distributed between the first semiconductor layer and the second semiconductor layer.
Option 2: wherein a cap layer is distributed between the gate electrode and the second semiconductor layer; the gate electrode is electrically isolated from the cap layer by the dielectric layer.
Option 3: wherein a cap layer is distributed between the gate electrode and the second semiconductor layer; the epitaxial structure further comprises an insertion layer distributed between the first semiconductor layer and the second semiconductor layer.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein a cap layer is distributed between the gate electrode and the second semiconductor layer; the gate electrode is electrically isolated from the cap layer by the dielectric layer – in Option 2.
Regarding claim 12, the limitation "a gate foot" in Line L2, renders the claim indefinite because the antecedent basis is unclear as to whether “a gate foot" (Line L2) refers to a new gate foot or “the gate foot” previously cited in Line L8 of claim 1. In the purpose of compact prosecution, "a gate foot" has been interpretated as the gate foot.
Regarding claim 12, the limitation "a gate " in Line L5, renders the claim indefinite because the antecedent basis is unclear as to whether “a gate " (Line L5) refers to a new gate or “the gate foot” previously cited in Line L8 of claim 1. In the purpose of compact prosecution, "a gate" has been interpretated as the gate foot.
Regarding claim 12, the limitation "and/or" in Line 10, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 12 results in the following options:
Option 1: a size of the gate cap in a direction of a source-drain channel is larger than a size of the gate foot in the direction of the source-drain channel, and the size of the gate foot in the direction of the source-drain channel is smaller than or equal to a length of the carrier channel; the gate electrode is a T-type gate; and the gate electrode is electrically isolated from the second semiconductor layer by the dielectric layer;
Option 2: a size of the gate cap in a direction of a source-drain channel is larger than a size of the gate foot in the direction of the source-drain channel, and the size of the gate foot in the direction of the source-drain channel is smaller than or equal to a length of the carrier channel; the gate electrode is a T-type gate;
Option 3: a size of the gate cap in a direction of a source-drain channel is larger than a size of the gate foot in the direction of the source-drain channel, and the size of the gate foot in the direction of the source-drain channel is smaller than or equal to a length of the carrier channel; the gate electrode is electrically isolated from the second semiconductor layer by the dielectric layer.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – a size of the gate cap in a direction of a source-drain channel is larger than a size of the gate foot in the direction of the source-drain channel, and the size of the gate foot in the direction of the source-drain channel is smaller than or equal to a length of the carrier channel; the gate electrode is a T-type gate; and the gate electrode is electrically isolated from the second semiconductor layer by the dielectric layer;-- in Option 1.
Regarding claim 13, the limitation "and/or" in Lines L3 and L6, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 13 results at least in the following options:
Option 1: wherein a dielectric layer is arranged between the gate electrode and the heterojunction;
and the dielectric layer is further configured for obstructing the gate electrode and the high resistance region, or the gate electrode is directly isolated from the high resistance region by air;
and the dielectric layer further extends and covers a surface of the epitaxial structure, and the source electrode and the drain electrode are matched with the epitaxial structure through corresponding windows formed on the dielectric layer.
Option 2: wherein a dielectric layer is arranged between the gate electrode and the heterojunction;
and the dielectric layer is further configured for obstructing the gate electrode and the high resistance region, or the gate electrode is directly isolated from the high resistance region by air.
Option 3: wherein a dielectric layer is arranged between the gate electrode and the heterojunction;
and the dielectric layer further extends and covers a surface of the epitaxial structure, and the source electrode and the drain electrode are matched with the epitaxial structure through corresponding windows formed on the dielectric layer.
Option 4: wherein a dielectric layer is arranged between the gate electrode and the heterojunction;
Option 5: wherein the dielectric layer is further configured for obstructing the gate electrode and the high resistance region, or the gate electrode is directly isolated from the high resistance region by air.
Option 6: wherein the dielectric layer further extends and covers a surface of the epitaxial structure, and the source electrode and the drain electrode are matched with the epitaxial structure through corresponding windows formed on the dielectric layer.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein a dielectric layer is arranged between the gate electrode and the heterojunction;
and the dielectric layer is further configured for obstructing the gate electrode and the high resistance region, or the gate electrode is directly isolated from the high resistance region by air;
and the dielectric layer further extends and covers a surface of the epitaxial structure, and the source electrode and the drain electrode are matched with the epitaxial structure through corresponding windows formed on the dielectric layer—in Option 1.
Regarding claim 14, the limitation "and/or" in Line 4, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 14 results in the following options:
Option 1: wherein the high resistance region is formed by a secondary epitaxial growth, or by transforming a local region of the heavily doped region; and an interface between the heavily doped region and the high resistance region is regulated by mutant doping or gradual doping.
Option 2: wherein the high resistance region is formed by a secondary epitaxial growth, or by transforming a local region of the heavily doped region.
Option 3: wherein an interface between the heavily doped region and the high resistance region is regulated by mutant doping or gradual doping.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein the high resistance region is formed by a secondary epitaxial growth, or by transforming a local region of the heavily doped region –in Option 2.
Regarding claim 16, the limitation "and/or" in Lines L2, L5, L7, and L9, renders the claim indefinite because one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “and/or” is defined as "a function word to indicate that two words or expressions are to be taken together or individually” (see Merriam-webster.com).
Claim 16 results at least in the following options:
Option 1: wherein a material of the epitaxial structure comprises III-V group compounds;
and, the high-electron-mobility transistor structure comprises a nitrogen polar high-electron-mobility transistor (HEMT) device structure or an HEMT device structure having a back barrier structure;
and, a high-electron-mobility structure is of a depletion-mode device structure or an enhanced device structure;
and, the high-electron-mobility structure further comprises a substrate where the epitaxial structure is formed;
and, the epitaxial structure further comprises a buffer layer distributed between the substrate and the first semiconductor layer.
Option 2: wherein a material of the epitaxial structure comprises III-V group compounds;
and, the high-electron-mobility transistor structure comprises a nitrogen polar high-electron-mobility transistor (HEMT) device structure or an HEMT device structure having a back barrier structure;
and, a high-electron-mobility structure is of a depletion-mode device structure or an enhanced device structure;
and, the high-electron-mobility structure further comprises a substrate where the epitaxial structure is formed.
Option 3: wherein a material of the epitaxial structure comprises III-V group compounds; and, the high-electron-mobility transistor structure comprises a nitrogen polar high-electron-mobility transistor (HEMT) device structure or an HEMT device structure having a back barrier structure;
and, a high-electron-mobility structure is of a depletion-mode device structure or an enhanced device structure;
and, the epitaxial structure further comprises a buffer layer distributed between the substrate and the first semiconductor layer.
Option 5: wherein a material of the epitaxial structure comprises III-V group compounds;
Option 6: wherein the high-electron-mobility transistor structure comprises a nitrogen polar high-electron-mobility transistor (HEMT) device structure or an HEMT device structure having a back barrier structure;
and, a high-electron-mobility structure is of a depletion-mode device structure or an enhanced device structure;
and, the high-electron-mobility structure further comprises a substrate where the epitaxial structure is formed;
and, the epitaxial structure further comprises a buffer layer distributed between the substrate and the first semiconductor layer.
Thus, the limitation “and/or" is unclear because defining which combination of the stated limitations is necessary or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim “and/or” limitation is being interpretated as – wherein a material of the epitaxial structure comprises III-V group compounds;
and, the high-electron-mobility transistor structure comprises a nitrogen polar high-electron-mobility transistor (HEMT) device structure or an HEMT device structure having a back barrier structure;
and, a high-electron-mobility structure is of a depletion-mode device structure or an enhanced device structure;
and, the high-electron-mobility structure further comprises a substrate where the epitaxial structure is formed.—in Option 2.
Regarding claim 16, the limitation " a high-electron-mobility structure" in Line L5, renders the claim indefinite because the antecedent basis is unclear as to whether “a high-electron-mobility structure" (Line L5) refers to a new a high-electron-mobility structure or “the a high-electron-mobility transistor structure” previously cited in Line L1 of claim 1. In the purpose of compact prosecution, "a high-electron-mobility structure" has been interpretated as the high-electron-mobility transistor structure.
Claim 26 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: how to use the high-electron-mobility transistor structure to fabricate a power amplifier, a radio frequency device, a communication device, or an electronic device. The use claim is then indefinite because it merely recites a use without any active, positive steps delimiting how this use is actually practiced. See MPEP § 2173.05(q).
The balance of claims are rejected for being dependent upon an already rejected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The claimed invention of claim 26 is directed to non-statutory subject matter. The claim(s) 26 does/do not fall within at least one of the four categories of patent eligible subject matter because claim 26 states “ a use method” in Line L1 but fails to include a step on how to use the HEMT, therefore it is not a proper use claim. "Use" claims that do not purport to claim a process, machine, manufacture, or composition of matter fail to comply with 35 U.S.C. 101. See MPEP § 2173.05(q).
Therefore, claim 26 is rejected under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) [1] is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS.
Regarding claim 1, NPLHuang13 discloses a high-electron-mobility transistor structure (Abstract Lines L1-3), comprising:
an epitaxial structure(AlN/GaN grown by MOCVD so epitaxial structure-pp3019 [Introduction] Column C2 L22-23, Fig 1(b)), comprising
a heterojunction (GaN/AlN/GaN junction-Abstract L2) consisting of
a first semiconductor layer (first layer GaN-Abstract L2) and
a second semiconductor layer(second layer AlN-Abstract L2),
a carrier channel being formed between the first semiconductor layer and the second semiconductor layer(AlN barrier maximizing 2DEG density so carrier channel, and allowing good control over channel carrier so the carrier channel is just under the layer AlN, consequently is between the first layer and the second layer-pp3019 [Introduction] C1L15-C2L1); and
a source electrode (Fig 2(i)),
a drain electrode (Fig 2(i)), and
a gate electrode (Fig 2(i)),
wherein the source electrode, the drain electrode, and the gate electrode are matched with the epitaxial structure (source/gate/drain electrodes are matched with the AlN/GaN layers-Fig 2(i)), and
the source electrode being electrically connected with the drain electrode through the carrier channel (Source electrode and Drain electrode are part of an equivalent circuit and are connected through the carrier channel-Fig 1(b));
wherein, a coincidence rate between an orthographic projection of the-a gate foot of the gate electrode on the first semiconductor layer and an orthographic projection of the second semiconductor layer on the first semiconductor layer is more than 80% (SiO2 is 500 nm-thick covered by a 50nm-thick SiNx layer so the total thickness is 600nm-C1 L21, Fig 2(b); after etching the AlN/GaN is also 600nm-thick being aligned with the SiO2/ SiNx-Fig 2(c); SiO2 is removed followed by Al2O3 deposition of 6nm so the recess is 488 nm-thick (500-12=488nm)-C2 L22-23, Fig 2(h); deposition of gate electrode in recess so gate electrode foot is 488nm wide-Fig 2(i); the orthographic projection of the gate foot so projection vertically on the first semiconductor GaN, is its width; The orthographic projection of the second semiconductor layer AlN is also it width, so the ratio between the width of the AlN/GaN layers and the gate-electrode-foot width is then 488nm/600nm=81%, so larger than 80%-Examiner's annotated Fig 2).
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Regarding claim 2, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the orthographic projection of the gate foot on the first semiconductor layer coincides with the orthographic projection of the second semiconductor layer on the first semiconductor layer (dashed line rectangle shows the orthographic projection of the gate foot on the first semiconductor layer GaN; the second semiconductor layer AlN is aligned with the First semiconductor layer GaN so its orthographic projection is the top surface of the first semiconductor layer GaN; the orthographic projection of the gate foot on the first semiconductor layer coincides with the orthographic projection of the second semiconductor layer on the first semiconductor layer-Examiner's annotated Fig 2 with a focus on Fig 2(i)); and/or,
the carrier channel is distributed in a region covered by the orthographic projection of the gate electrode on the epitaxial structure (GaN carrier channel being in a region covered by orthographic projection shown by the dashed line rectangle-Examiner's annotated Fig 2).
Regarding claim 3, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the epitaxial structure further comprises an ohmic contact layer (ohmic contact layer (n+ GaN interface+SiNx)-Fig 2(d)),
the ohmic contact layer is in contact with the carrier channel (ohmic contact layer (n+ GaN interface+SiNx ) is on each side so in contact with the carrier channel GaN -Fig 2(d)),
wherein both the source electrode and the drain electrode are arranged on the ohmic contact layer (both source electrode S and drain electrode D arranged on ohmic contact layer (n+ GaN interface+SiNx)-Fig 2(d)) and
form ohmic contact with the ohmic contact layer (Ti-based alloy being chosen as the ohmic contact metal for n+ GaN layer, so source/drain electrodes being in ohmic contact with the ohmic contact layer (n+ GaN interface+SiNx)-p3020 [III] C2 L 31-32); and
the ohmic contact layer and the carrier channel form ohmic contact (the ohmic contact layer (n+ GaN interface+SiNx) and
the carrier channel GaN being in contact, so forming ohmic contact-Fig 1(b)).
Regarding claim 4, NPLHuang13 discloses all the elements of claim 3, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein a groove is distributed in a region of the ohmic contact corresponding to the gate electrode (Groove in a region of ohmic contact corresponding to the gate electrode (fig 1(b), Fig 2(h), Fig 2(i)),
at least a bottom of the gate foot and the second semiconductor layer are arranged in the groove (bottom of gate and second semiconductor layer GaN being arranged in the groove-Examiner's annotated Fig 2 (i)); and/or,
the gate electrode is electrically isolated from the ohmic contact layer by a dielectric layer (gate electrode isolated by dielectric layer high-k Al2O3 from ohmic layer n+ GaN interface-Fig 2 (i), Fig 1(b)), or
the gate electrode is isolated from the ohmic contact layer by air.
Regarding claim 5, NPLHuang13 discloses all the elements of claim 4, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein an included angle of 60-90° is formed between a side wall of the groove and a surface of the first semiconductor layer (The electrode is a T-shape electrode so including a 90 degree formed between a side wall of the groove and a surface of the first semiconductor layer GaN-Fig 1(b)); and/or,
the-a gate cap of the gate electrode covers the dielectric layer on the groove (The electrode is a T-shape electrode so including a horizontal part interpretated as the gate cap covering the dielectric layer Al2O3-Fig 1(b)).
Regarding claim 6, NPLHuang13 discloses all the elements of claim 3, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the ohmic contact layer (interface n+ GaN-Fig 1(b)) comprises
a heavily doped region (heavily doped region n+ Gan-Fig 1 (b)) and
a high resistance region (High resistance region SiNx-Fig1(b), p3020 [III] C2 L 31-32);
the heavily doped region is arranged on the heterojunction (n+ GaN region on heterojunction AlN/GaN-Fig 1(b)) and
forms ohmic contact with the carrier channel (n+ GaN region in contact with carrier channel GaN having resistances Rs and Rd so forming ohmic contact-Fig 1(b)),
the source electrode and the drain electrode form ohmic contact with the heavily doped region (Ti-based alloy being chosen as the ohmic contact metal for n+ GaN layer, so source/drain electrodes being in ohmic contact with the heavily doped region n+ GaN-p3020 [III] C2 L 31-32),
the high resistance region is arranged on the heavily doped region (High resistance region S or D arranged on heavily doped region n+ GaN-Fig1(b), p3020 [III] C2 L 31-32),
the source electrode is isolated from the gate electrode by the high resistance region (The high resistance SiNx is between Source and gate electrode, so isolating one from the other-Examiner's annotated Fig 2 (i), Fig 1(b)), and
the drain electrode is isolated from the gate electrode by the high resistance region (the high resistance SiNx is between Drain and gate electrode, so isolating one from the other-Examiner's annotated Fig 2 (i), Fig 1(b)); or
the gate is directly isolated from the heavily doped ohmic contact layer by utilizing air.
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Regarding claim 7, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein an upper surface of the heavily doped region is higher than a surface of the carrier channel (upper surface of the heavily doped region n+ GaN is higher than a surface of the carrier channel GaN-Examiner's annotated Fig 2(i)) ; and/or,
the heavily doped region comprises
a first heavily doped region matched with the source electrode (first heavily doped region Left n+ GaN matched with the source electrode S- Examiner's annotated Fig 2(i)) and
a second heavily doped region matched with the drain electrode (second heavily doped region Right n+ GaN matched with the Drain electrode D- Examiner's annotated Fig 2(i)),
the first heavily doped region and the second heavily doped region are respectively located at two sides of the second semiconductor layer (first heavily doped region Left n+ GaN and second heavily doped region Left n+ GaN located on each side of the second semiconductor layer Gan of the Heterostructure AlN/GaN- Examiner's annotated Fig 2(i)),
the high resistance region comprises
a first high resistance region matched with the source electrode (first high resistance region Left SiNx matched with the source electrode S- Examiner's annotated Fig 2(i)) and
a second high resistance region matched with the drain electrode (second high resistance region Right SiNx matched with the Drain electrode D- Examiner's annotated Fig 2(i)), and
at least partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region ( partial first high resistance region penetrating first high resistance region Left SiNx, and partial second high resistance region penetrating second high resistance region Right SiNx so at least partial regions of the first high resistance region and the second high resistance region penetrate through the first high resistance region and the second high resistance region L/R SiNx-Examiner's annotated Fig 2(i)) and
then is in ohmic contact with the first heavily doped region and the second heavily doped region (the first high resistance region and the second high resistance region L/R SiNx are in direct contact with the first heavily doped region Right n+ Gan and the second heavily doped region Left n+ GaN, so in ohmic contact with them-Examiner's annotated Fig 2(i)).
Regarding claim 8, NPLHuang13 discloses all the elements of claim 7, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the carrier channel is a two-dimensional electron gas channel (Carrier Channel GaN capped by barrier AlN lead to maximize 2D electron gas so the carrier channel is a two-dimensional electron gas channel-pp 3019 [Introduction] C1 L15-19),
the second semiconductor layer is arranged on the first semiconductor layer (Second semiconductor layer AlN arranged on First semiconductor layer GaN-Examiner's annotated Fig 2) , and
the first and second heavily doped regions are of n type (the first and second heavily doped regions L/R n+ GaN so n type-Examiner's annotated Fig 2); or,
the carrier channel is a two-dimensional hole gas channel, and the first and second heavily doped regions are of p type.
Regarding claim 9, NPLHuang13 discloses all the elements of claim 8, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the first semiconductor layer comprises
a first region and a second region (GaN comprising a first and second regions-Examiner's annotated Fig 2(i)),
a bulge portion is formed in the first region (Examiner's annotated Fig 2(i)),
the second semiconductor layer is arranged on the bulge portion (the second semiconductor layer AlN arranged on the bulge portion-Examiner's annotated Fig 2(i)),
the first heavily doped region and the second heavily doped region are arranged on the second region (first heavily doped region and second heavily doped region L/R n+ GaN arranged on the second region-Examiner's annotated Fig 2(i)) and
distributed at two sides of the bulge portion (first heavily doped region and second heavily doped region L/R n+ GaN arranged on each side of the bulge-Examiner's annotated Fig 2(i).
Regarding claim 10, NPLHuang13 discloses all the elements of claim 7, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein a cap layer is distributed between the gate electrode and the second semiconductor layer (Cap layer GaN on second conductor layer AlN-Examiner's annotated Fig 2(i)).
the gate electrode is electrically isolated from the cap layer by the dielectric layer (Gate electrode electrically isolated from cap layer GaN by dielectric layer Al2O3 (Fig 1); and/or,
the epitaxial structure further comprises an insertion layer distributed between the first semiconductor layer and the second semiconductor layer.
Regarding claim 11, NPLHuang13 discloses all the elements of claim 10, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the epitaxial structure comprises a Ga polar surface (pp3019 [Introduction] C2 L3-4) or
an N polar surface (pp3019 [Introduction] C2 L3-4).
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Regarding claim 12, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the gate electrode comprises a gate cap and a gate foot (Fig 1(b)),
wherein the gate cap is arranged on the high resistance region and supported by the high resistance region (Gate cap on high resistance region SiNx-Examiner's annotated Fig 2(i)),
the gate foot is arranged in the epitaxial structure (gate foot between the n+ GaN L/R regions grown by MOCVD so in the epitaxial structure-Examiner's annotated Fig 2(i), pp3019 [Introduction] Column C2 L22-23), and
the carrier channel is distributed right under the gate foot (Carrier channel GaN right under the gate foot-Examiner's annotated Fig 2(i)); or
the gate is directly isolated from the heavily doped ohmic contact layer by utilizing airs;
a size of the gate cap in a direction of a source-drain channel is larger than that a size of the gate foot in the direction of the source-drain channel (the gate electrode is T-shaped so the width of the cap is larger than the width of the foot in the horizontal direction which has been interpretated as the source-drain channel direction-Fig 2(i)), and
the size of the gate foot in the direction of the source-drain channel is smaller than or equal to a length of the carrier channel (Width of the gate foot is smaller than or equal to the length of the carrier channel GaN in the horizontal direction-Examiner's annotated Fig 2(i));
the gate electrode is a T-type gate (the gate electrode is T-shaped-Examiner's annotated Fig 2(i)); and/or,
the gate electrode is electrically isolated from the second semiconductor layer by the dielectric layer (gate electrode is electrically isolated from second semiconductor AlN by dielectric layer Al2O3-Fig 1); and
a side wall dielectric layer is also formed between the side wall of the gate foot and the high resistance region (side wall dielectric layer Al2O3 formed on the vertical side wall of gate foot and high resistance SiNx-Fig 1).
Regarding claim 13, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein a dielectric layer is arranged between the gate electrode and the heterojunction (dielectric layer Al2O3 between gate electrode and heterojunction Cap layer GaN/2nd semiconductor AlN/1st semiconductor GaN-Fig 1); and/or,
the dielectric layer is further configured for obstructing the gate electrode and the high resistance region (dielectric layer Al2O3 vertically between gate electrode and high resistance region SiNx so obstructing them-Fig 1), or
the gate electrode is directly isolated from the high resistance region by air; and/or,
the dielectric layer further extends and covers a surface of the epitaxial structure (dielectric layer Al2O3 horizontally between gate electrode and high resistance region SiNx so extending and covering the epitaxial structure-Fig 1), and
the source electrode and the drain electrode are matched with the epitaxial structure through corresponding windows formed on the dielectric layer(Source electrode S and Drain electrode D matched through opening to the epitaxial structure-Fig 1).
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Regarding claim 14, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein the high resistance region is formed by a secondary epitaxial growth (High resistance region SiNx formed by a secondary epitaxial growth-Examiner's annotated Fig 2), or
by transforming a local region of the heavily doped region; and/or,
an interface between the heavily doped region and the high resistance region is regulated by mutant doping or gradual doping.
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Regarding claim 16, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a high-electron-mobility transistor structure
wherein a material of the epitaxial structure comprises III-V group compounds (epitaxial layer AlN/GaN so III-V group-Fig 1); and/or,
the high-electron-mobility transistor structure comprises a nitrogen polar high-electron-mobility transistor (HEMT) device structure (pp3019 [Introduction] C2 L3-4) or
an HEMT device structure having a back barrier structure; and/or,
a high-electron-mobility structure is of a depletion-mode device structure or
an enhanced device structure (pp3019 [Design of Gate-last Device] C2 L 1-2); and/or,
the high-electron-mobility structure further comprises
a substrate where the epitaxial structure is formed (Si Substrate with epitaxial structure GaN/AlN/GaN-Fig 1); and/or,
the epitaxial structure further comprises
a buffer layer distributed between the substrate and the first semiconductor layer.
Regarding claim 26, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a use method of the high-electron-mobility transistor structure as claimed is claim 1, comprising
fabricating a power amplifier, a radio frequency device, a communication device, or an electronic device (GaN high-electron mobility transistors (HEMTs) practical advantages in applications of RF/millimeter-wave power amplifier and power switching so use for fabricating power amplifier-pp3019 [Introduction] C1 L 1-4)
Regarding claim 27, NPLHuang13 discloses all the elements of claim 1, as noted above.
NPLHuang13 further discloses a power amplifier, comprising
the high-electron-mobility transistor structure according to claim 1 (GaN high-electron mobility transistors (HEMTs) practical advantages in applications of RF/millimeter-wave power amplifier and power switching so power amplifier comprising HEMT-pp3019 [Introduction] C1 L 1-4).
Regarding claim 28, NPLHuang13 discloses all the elements of claim 27, as noted above.
NPLHuang13 further discloses a power amplifier comprising
a power amplifier with a radio frequency wave band, a millimeter wave band or a terahertz wave band (GaN high-electron mobility transistors (HEMTs) practical advantages in applications of RF/millimeter-wave power amplifier and power switching so power amplifier with radio frequency wave band-pp3019 [Introduction] C1 L 1-4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3019-3024, Oct. 2013-NPLHuang13) from IDS in view of Grote et al. (US 20220376060 A1-Grote60).
Regarding claim 15, NPLHuang13 discloses all the elements of claim 6, as noted above.
NPLHuang13 does not disclose a high-electron-mobility transistor structure further comprising
an isolation region formed in the epitaxial structure and
configured for isolating an active region.
Grote60 teaches a high-electron-mobility transistor structure further comprising
an isolation region formed in the epitaxial structure (isolation region 120 formed in the semiconductor substrate 110 to define an active zone 125; implantation procedure on epitaxial layers create 122 from 120, so isolation region formed in the epitaxial structure-[0021] L1-9) and
configured for isolating an active region (isolation region 120 formed in the semiconductor substrate 110 to define an active zone 125-[0021] L1-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the high-electron-mobility transistor structure of NPLHuang13, as taught byGrove60 for the purpose of creating a 2-DEGby disposing the channel layer over the barrier layer (Grove60: [0020] L27-30).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hickman et al. (US20200388701 A1-Hickman01) teaches a high-electron-mobility transistor structure (Fig 1), comprising: an epitaxial structure (GaN/AlN/GaN/AlN-Fig 1), comprising a heterojunction (GaN/AlN/GaN-Fig 1) consisting of a first semiconductor layer (AlN-Fig 1) and a second semiconductor layer (AlN-Fig 1), a carrier channel (GaN-Fig 1) being formed between the first semiconductor layer and the second semiconductor layer (AlN/GaN/AlN-Fig 1); and a source electrode (Ti/Au Left electrode-Fig 12), a drain electrode (Ti/Au Right electrode-Fig 12), and a gate electrode (Ti/Au T-shape middle electrode-Fig 12).
Moon et al (US-20210013307-A1-Moon07) teaches a high-electron-mobility transistor structure (Fig 1), comprising: an epitaxial structure (AlN/AlGaN/GaN/AlN -Fig 5), comprising a heterojunction (AlN/AlGaN/GaN/AlN-Fig 5) consisting of a first semiconductor layer (AlGaN-Fig 5) and a second semiconductor layer (AlN-Fig 5), a carrier channel (GaN-Fig 5) being formed between the first semiconductor layer and the second semiconductor layer (AlN/AlGaN/GaN/AlN -Fig 5); and a source electrode (42-Fig 5), a drain electrode (46-Fig 5), and a gate electrode (50 T-shape middle electrode-Fig 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 03/05/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812