Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1: states in line 9: “a first electrode”; however, in line 7, claim 1 states: “a first electrode”. It is not clear whether, it is the same first electrode.
For purpose of examination, line 9 of claim 1 will be treated as: “the first electrode”.
Proper correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iguchi (US 2018/0358339 A1).
Regarding independent claim 1: Iguchi teaches (e.g., Fig. 15 and Fig. 4; using Fig. 3 and Figs. 9A-9I for element description) a display device including a semiconductor light emitting device comprising:
a substrate ([0111]: 200);
a first assembly wiring ([0093]: 19) and a second assembly wiring ([0093]: 20) alternately arranged on the substrate (200) and spaced apart from each other;
a planarization layer ([0097], [0135]: layer 60/61 maintains the light device layer in a planar surface) disposed on the first assembly wiring (19) and the second assembly wiring (20) and having a first opening (region between consecutive layers 60/61); and
a semiconductor light emitting device ([0188]: 11) having a first electrode ([0084], [0093]: 41), disposed inside the first opening, and overlapping the first assembly wiring (19) and the second assembly wiring (20),
wherein the first electrode (19) of the semiconductor light emitting device (11) is electrically connected to one of the first assembly wiring and the second assembly wiring (19).
Regarding claim 2: Iguchi teaches the claim limitation of the display device, including the semiconductor light emitting device according to claim 1, on which this claim depends, further comprising
an insulating layer ([0339]: 250) between the first assembly wiring (19) and the first electrode (41) of the semiconductor light emitting device, and
wherein the second assembly wiring (20) is exposed from the insulating layer (250) at the first opening (spaced occupied by the semiconductor light emitting device 11).
Regarding claim 8: Iguchi teaches the claim limitation of the display device, including the semiconductor light emitting device according to claim 1, on which this claim depends,
wherein the first assembly wiring (19) and the second assembly wiring (20) are arranged on a same plane (horizontal plane).
Regarding claim 11: Iguchi teaches the claim limitation of the display device, including the semiconductor light emitting device according to claim 1, on which this claim depends,
further comprising a ground pad electrically connected to an active area of the substrate ([0103], [0106], [0191]: point of connection with ground line 115 considered as ground pad).
Claims 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2019/0051242 A1).
Regarding independent claim 15: Lee teaches (e.g., Figs. 1, 3-4; Fig. 3 is a portion of the display; [0030]) a display device including a semiconductor light emitting device comprising:
a substrate ([0070]-[0071]: 100) having a plurality of sub-pixels defined ([0043] and [0045]);
a first assembly wiring ([0070]: 201) arranged along a plurality of sub-pixels ([0043], [0045]: PX represents a subpixel of the display device) arranged on a same line among the plurality of sub-pixels;
a second assembly wiring ([0070]: 202) arranged along the plurality of sub-pixels arranged on the same line among the plurality of sub-pixels and adjacent to each of the first assembly wiring (201); and
a planarization layer ([0070] and [0085]: layer 500 ensures underlayers are planar) comprising a first opening ([0070] and [0085]: planarization layer 500 includes a left portion and a right portion and an opening between left portion and a right portion) and overlapping the first assembly wiring (201) and the second assembly wiring (202),
wherein each of the plurality of sub-pixels comprises a light emitting device ([0070], [0077] and [0085]: 300) disposed in the first opening and electrically connected to the second assembly wiring (Fig. 4; second assembly wiring 202).
Regarding claim 16: Lee teaches the claim limitation of the display device including the semiconductor light emitting device according to claim 15, on which this claim depends,
wherein the light emitting device (300) is bonded to the second assembly wiring (202) at the first opening (region between left portion and a right portion 500).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0051242 A1) in view of Zhang et al. (US 2017/0069609 A1).
Regarding claim 19: Lee teaches the claim limitation of the display device including the semiconductor light emitting device according to claim 15, on which this claim depends,
Lee does not expressly teach that the display device further comprises a ground pad electrically connected to an active area of the substrate.
Zhang teaches (e.g., Fig. 7A) a display device comprising a substrate ([0068]: 102);
Zhang further teaches a ground pad ([0068]-[0069]: 704 ) electrically connected to an active area ([0065]-[0066]: 106) of the substrate ([0068]: 102).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Lee, the ground pad electrically connected to an active area of the substrate, as taught by Zhang, for the benefits of protecting the integrated circuit from high voltage electrical damage.
Allowable Subject Matter
Claims 3-7, 9-10, 12-14, 17-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcoming the CFR 112(b) rejection.
Regarding claim 3: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor light emitting device comprising:
“a first clad layer in contact with the first conductive layer, and
wherein the second assembly wiring comprises a second conductive layer disposed on the insulating layer,
a second clad layer in contact with the second conductive layer, and wherein the first electrode of the semiconductor light emitting device is in contact with the second clad layer”.
Claims 4-7 depend from claim 3, and therefore, are allowable for the same reason as claim 3 .
Regarding claim 9: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor light emitting device comprising:
“wherein a portion of the first assembly wiring and a portion of the second assembly wiring overlap the first opening, and
wherein a sum of a width of a portion of the first assembly wiring in the first opening and a width between the first assembly wiring and the second assembly wiring in the first opening is smaller than a height of the light emitting device”.
Regarding claim 10: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor light emitting device comprising:
“further comprising a protrusion configured to protrude from a side wall of the planarization layer in the first opening and configured to cover a portion of the first assembly wiring and a portion of the second assembly wiring”.
Regarding claim 12: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor light emitting device comprising:
“wherein the first assembly wiring vertically overlaps the second assembly wiring, and wherein the second assembly wiring comprises an electrode hole in an area vertically overlapping with the first assembly wiring”.
Regarding claim 13: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor light emitting device comprising:
“wherein the first assembly wiring comprises a first conductive layer and a first clad layer on the first conductive layer,
wherein the second assembly wiring comprises a second conductive layer and a second clad layer on the second conductive layer,
wherein the first clad layer comprises a first-first clad layer and a first-second clad layer extending from the first-first clad layer,
wherein the second clad layer comprises a second-first clad layer and a second-second clad layer extending from the second-first clad layer, and wherein the first-second clad layer and the second-second clad layer are configured to overlap vertically”.
Claim 14 depends from claim 13, and therefore, is allowable for the same reason as claim 13 .
Regarding claim 17: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a display device including a semiconductor light emitting device comprising:
“wherein each of the first assembly wirings comprises a first conductive layer and a first clad layer electrically connected to the first conductive layer, wherein each of the second assembly wirings comprises a second conductive layer; and a second clad layer electrically connected to the second conductive layer, and wherein the first conductive layer and the first clad layer are made of different materials, and the second conductive layer and the second clad layer are made of different materials”.
Claim 18 depends from claim 17, and therefore, is allowable for the same reason as claim 17.
Regarding claim 20: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a display device including a semiconductor light emitting device comprising:
“wherein the first assembly wiring is configured to vertically overlap the second assembly wiring, and wherein the second assembly wiring comprises an electrode hole in a region vertically overlapping the first assembly wiring”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812