Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6, 9-11, & 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Mangtani DE10196942 using PE2E search for translation.
Per claim 1 Mangtani teaches a circuit assembly (see fig.4B) comprising: an insulated metal substrate (IMS) (15, see fig.4B; [0049]); a switching device (20 and/or 21; [0050], “power semiconductor chips/plates have transistors which are switching devices”) located on the IMS (see fig.4B); and a printed circuit board (PCB) (13) directly attached and electrically connected to the IMS ([0002], [0004]-[0005], “Next a PCB is attached to the base shell, and contraction wire connections are made between the silicon semiconductor plate and the substrate to the PCB”, [0048], [0050], [0054], “it is understandable that the wire contact surface of the IMS 15 and the PCB 13 are located at different heights”, [0058], “The semiconductor plate, the substrate (IMS), and the PCB are then connected to each other in a suitable manner by wire contacts, and the subassembly is electrically tested”, Examiner asserts that from the above paragraphs the IMS is disclosed to have upper copper layer, which can be patterned to form conductive mounting pads to which power semiconductor wafers, such as… the semiconductor plates 20 and 21, can be attached and connected to each other, the IMS and PCB are disclosed to be electrically conductive via the wire contacts, the last paragraph asserts that the subassembly of the semiconductor plate, IMS and PCB are all connected and electrically tested, thus teaching an electrical connection between the IMS, PCB and the semiconductor plate”) such that opposing surfaces of the IMS and the PCB directly contact with no gap therebetween (see fig.4B) and including a cutout that receives the switching device (see fig.4B; [0020]-[0022]).
Per claim 3 Mangtani teaches the circuit assembly according to claim 1, wherein the PCB routes power and signals to the switching device ([0050]).
Per claim 6 Mangtani teaches the circuit assembly according to claim 1, further comprising a heatsink (30) attached to the IMS (15, see fig.4B).
Per claim 9 Mangtani teaches the circuit assembly according to claim 1, wherein the PCB (13) is surface mounted to the IMS (15, see fig.4B) to electrically connect the PCB to the IMS ([0050], [0053], see fig.4B).
Per claim 10 Mangtani teaches the circuit assembly according to claim 1, wherein the PCB (13) is surface mounted to the IMS (15, see fig.4B) such that power is routed among the PCB, the IMS, and the switching device ([0004]-[0005], [0050], [0053]).
Per claim 11 Mangtani teaches the circuit assembly according to claim 1, wherein the PCB is surface mounted to the IMS such that a gate signal from the PCB is applied to the switching device through the IMS ([0002]-[0004], & [0050], see fig.4B).
Per claim 15 Mangtani teaches the circuit assembly according to claim 6, wherein the PCB is surface mounted to the IMS to electrically connect the PCB to the IMS ([0050], [0053], see fig.4B).
Per claim 16 Mangtani teaches the circuit assembly according to claim 6, wherein the PCB is surface mounted to the IMS such that power is routed among the PCB, the IMS, and the switching device ([0004]-[0005], [0050], [0053]).
Per claim 17 Mangtani teaches the circuit assembly according to claim 6, wherein the PCB is surface mounted to the IMS such that a gate signal from the PCB is applied to the switching device through the IMS ([0050], [0053], see fig.4B).
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mangtani DE10196942 using PE2E search for translation in view of BYUN US2022/0264738.
Per claim 5 Mangtani teaches the circuit assembly according to claim 1,
Mangtani does not explicitly teach wherein the PCB further includes negative-temperature-coefficient temperature sensing circuitry.
BYUN however teaches wherein a PCB further includes negative-temperature-coefficient temperature sensing circuit (Abstract).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have a negative-temperature-coefficient temperature sensing circuitry as taught by BYUN in the circuit assembly of Mangtani, because it enables high sensitivity to temperature changes, it is compact size and it has a fast response time, thus ensuring proper heat detection and cooling of the circuit assembly.
Per claim 12 Mangtani in view of BYUN teaches the circuit assembly according to claim 5, wherein the PCB (13) is surface mounted to the IMS (15, see fig.4B) to electrically connect the PCB to the IMS ([0050], [0053], see fig.4B).
Per claim 13 Mangtani in view of BYUN teaches the circuit assembly according to claim 5, wherein the PCB is surface mounted to the IMS such that power is routed among the PCB, the IMS, and the switching device ([0004]-[0005], [0050], [0053]).
Per claim 14 Mangtani in view of BYUN teaches the circuit assembly according to claim 5, wherein the PCB is surface mounted to the IMS such that a gate signal from the PCB is applied to the switching device through the IMS ([0050], [0053], see fig.4B).
Claim(s) 8, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mangtani DE10196942 using PE2E search for translation in view of LEVY et al. US2017/0163257.
Per claim 8 Mangtani teaches the circuit assembly according to claim 1,
Mangtani does not explicitly teach wherein the switching device is a gallium nitride switching device.
LEVY et al. however discloses wherein a switching device is a gallium nitride switching device ([0004]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use gallium nitride as a switching device because of the superior electrical properties and faster switching speeds properties of gallium nitride.
Per claim 18 Mangtani in view of LEVY et al. teaches the circuit assembly according to claim 8, wherein the PCB is surface mounted to the IMS to electrically connect the PCB to the IMS ([0050], [0053], see fig.4B).
Per claim 19 Mangtani in view of LEVY et al. teaches the circuit assembly according to claim 8, wherein the PCB is surface mounted to the IMS such that power is routed among the PCB, the IMS, and the switching device ([0004]-[0005], [0050], [0053]).
Per claim 20 Mangtani in view of LEVY et al. teaches the circuit assembly according to claim 8, wherein the PCB is surface mounted to the IMS such that a gate signal from the PCB is applied to the switching device through the IMS ([0050], [0053], see fig.4B).
Response to Arguments
3. Applicant's arguments filed 07/16/26 have been fully considered but they are not persuasive.
Applicant asserts on page 1-2 of the remarks that the printed circuit board (PCB) directly attached and electrically connected to the IMS is not taught by the rejection dated 04/20/26.
Examiner disagree and asserts that Mangtani DE10196942 discloses in ([0002], [0004]-[0005], “Next a PCB is attached to the base shell, and contraction wire connections are made between the silicon semiconductor plate and the substrate to the PCB”, [0048], [0050], [0054], “it is understandable that the wire contact surface of the IMS 15 and the PCB 13 are located at different heights”, [0058], “The semiconductor plate, the substrate (IMS), and the PCB are then connected to each other in a suitable manner by wire contacts, and the subassembly is electrically tested”, Examiner asserts that from the above paragraphs the IMS is disclosed to have upper copper layer, which can be patterned to form conductive mounting pads to which power semiconductor wafers, such as… the semiconductor plates 20 and 21, can be attached and connected to each other, the IMS and PCB are disclosed to be electrically conductive via the wire contacts, the last paragraph asserts that the subassembly of the semiconductor plate, IMS and PCB are all connected and electrically tested, thus teaching an electrical connection between the IMS, PCB and the semiconductor plate”).
Email Communication
4. Applicant is encouraged to authorize the Examiner to communicate via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502, 502.05.
Conclusion
5. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A MATEY whose telephone number is (571)270-5648. The examiner can normally be reached Monday-Friday 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAYPRAKASH GANDHI can be reached at 5712723740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL A MATEY/Primary Examiner, Art Unit 2835
Prosecution Insights