DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 10-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations "a first electrode" and “a second electrode” in lines 10-11. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites semiconductor chip electrodes bonded to a conductive spacer surface in line 6. It is unclear if the first and second electrodes of lines 10-11 refer to the electrodes of line 6, or different/additional electrodes.
For the purpose of compact prosecution, the Examiner has interpreted claim 1 to mean:
“a semiconductor chip on which first and second electrodes are bonded onto an upper surface of the conductive spacer”, and
“wherein the conductive spacer comprises a first conductive spacer bonded to [[a]] the first electrode of the semiconductor chip, and [[a]] the second conductive spacer bonded to a second electrode of the semiconductor chip”.
Claims 8 has similar limitations to claim 1, and is rejected under 35 USC § 112(b) for the same reasons.
Claims 2-7 and 10-11 depend on claims 1 and 8, and are rejected under 35 USC § 112(b) for implicitly including the indefinite subject matter above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (PG Pub. No. US 2021/0013176 A1) in view of Tsukada et al. (PG Pub. No. US 2011/0080714 A1) and Osanai et al. (PG Pub. No. US 2015/0284296 A1).
Regarding claim 1, Lin teaches a power module (¶ 0028: 200) comprising:
a ceramic substrate (¶ 0030: 180, including substrate ceramic portion 181) on which an electrode pattern made of a metal (¶ 0030: conductive layer 182 comprising metal) is formed on at least one surface of a ceramic base material (fig. 2: 182 formed on at least one surface of 181);
a conductive spacer (¶ 0025: 50) having a lower surface that is bonded onto the electrode pattern of the ceramic substrate (fig. 2: in an inverted orientation, lower surface of 50 at least indirectly bonded onto 182);
a semiconductor chip (¶¶ 0025, 0047: die 30, including devices on a semiconductor substrate) on which electrodes (¶ 0025: 213 or 31) are bonded onto an upper surface of the conductive spacer (figs. 1-2: in an inverted orientation, 213/31 bonded to upper surface of 50); and
a coupling layer (¶ 0031: 214) configured to couple the electrode pattern of the ceramic substrate and the lower surface of the conductive spacer (fig. 2: in an inverted orientation, 214 couples 182 to lower surface of 50),
wherein the conductive spacer comprises a first conductive spacer bonded to a first electrode of the semiconductor chip (fig. 1: surface of 50 bonded to 31), and a second conductive spacer (fig. 2: module comprises at least two conductive spacers 50), and
wherein the power module comprises the first conductive spacers and the second conductive spacers that are respectively disposed symmetrically with respect to a center point of the at least one surface of the ceramic substrate (fig. 2: plurality of 50 disposed symmetric with respect to center point of 180).
Lin does not teach the second conductive spacer is bonded to a second electrode of the semiconductor chip, the first and second conductive spacers each comprise a respective plurality of conductive spacers, or the coupling material comprises brazing filler material configured to braze the electrode pattern of the ceramic substrate and the lower surface of the conductive spacer.
Tsukada teaches a power module (¶ 0061: 1000) including a first conductive spacer (¶ 0061: 32, similar to 50 of Lin) bonded to a first electrode (52, similar to 213 and/or 31 of Lin) of a semiconductor chip (fig. 1B: 32 bonded to 52 of semiconductor device 50, similar to 31 of Lin), and a second conductive spacer (¶ 0061: 33) bonded to a second electrode of the semiconductor chip (fig. 1B: 33 bonded to 53a of 50), the first and second conductive spacers each comprise a respective plurality of conductive spacers respectively disposed symmetrically with respect to a center point of a ceramic substrate surface (¶ 0078, fig. 1E: plurality of each 32 and 33 disposed symmetrically with respect to center point of ceramic substrate 100).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the conductive spacers of Lin with the plurality of Tsukada, as a means to provide an IPM (intelligent power module), improving functionality of the package.
Lin in view of Tsukada does not teach the coupling material comprises brazing filler material configured to braze the electrode pattern of the ceramic substrate and the lower surface of the conductive spacer.
Osanai teaches an electrode bonded/coupled to a ceramic substrate with brazing filler (¶ 0019: 12).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the coupling layer of Lin in view of Tsukada with brazing filler material, as a means to provide excellent bonding strength (Osanai, ¶ 0008) between the ceramic substrate and the conductive spacer of Lin.
Regarding claim 5, Lin in view of Tsukada and Osanai teaches the power module of claim 1, wherein the conductive spacer is formed of at least one of Cu, Mo, a CuMo alloy, and a CuW alloy (Lin, ¶ 0029).
Regarding claim 6, Lin in view of Tsukada and Osanai teaches the power module of claim 1, wherein the brazing filler layer is made of a material including at least one of Ag, Cu, AgCu, and AgCuTi (Osanai, ¶ 0036).
Regarding claim 7, Lin in view of Tsukada and Osanai teaches the power module of claim 1, wherein the electrodes of the semiconductor chip are bonded onto the upper surface of the conductive spacer by a bonding layer (Lin, figs. 1-2: 213) including a solder or a silver paste (Ag paste) (Lin, ¶ 0025).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tsukada and Osanai as applied to claim 1 above, and further in view of Otremba (PG Pub. No. US 2007/0040260 A1).
Regarding claim 2, Lin in view of Tsukada and Osanai teaches the power module of claim 1, comprising a conductive spacer (Lin, 50) and an electrode pattern (Lin, 182).
Lin in view of Osanai does not teach wherein an edge of the conductive spacer is disposed adjacent to an edge of the electrode pattern.
Otremba teaches a power semiconductor module (¶ 0003) including a conductive spacer (¶ 0040: 33) and an electrode pattern (¶¶ 0040-0042: S1, 19 and/or S2), wherein an edge of the conductive spacer is disposed adjacent to an edge of the electrode pattern (fig. 1: at least one edge of 33 adjacent to at least one edge of G1, D1, 29 and/or 39).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure an edge of the conductive spacer of Lin in view of Tsukada and Osanai adjacent to an edge of the electrode pattern, as a means to optimize contact area between the conductive spacer and the electrode pattern, enhancing thermal and/or electrical conduction (Otremba, ¶ 0035).
Furthermore, such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tsukada and Osanai as applied to claim 1 above, and further in view of Xue et al. (PG Pub. No. US 2014/0191334 A1).
Regarding claim 3, Lin in view of Tsukada and Osanai teaches the power module of claim 1, comprising:
a first conductive spacer (Lin, left 50 of stack 42, and/or Tsukada, 32); and
a second conductive spacer (Lin, right 50 of stack 46 and/or Tsukada, 33) disposed spaced apart from the first conductive spacer (Lin, fig. 2: right 50 spaced apart from left 50, and/or Tsukada, fig. 1E: 32 spaced apart from 33 in the x-axis direction), and having a side surface facing a side surface of the first conductive spacer (Lin, fig. 2: side surface of right 50 faces side surface of left 50, and/or Tsaukada, side surface of 33 faces side surface of 32).
Lin in view of Tsukada and Osanai does not teach the first conductive spacer in the form of an "L" shape, and disposed adjacent to an edge of the "L" shape on the electrode pattern.
Xue teaches a power semiconductor device (abstract) including a first conductive pad (¶ 0031: 201b) in the form of an "L" shape (¶ 0031 & fig. 3A: 201b comprises on L-shape), and disposed adjacent to an edge of the "L" shape on an electrode pattern (fig. 3A: 201b formed adjacent to an L-shaped edge of 201a), and a second conductive pad (¶ 0031: 202b) with a side surface facing a side surface of the first conductive pad (fig. 3A: side surface of 202b faces side surface of 201b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first conductive spacer of Lin in view of Tsukada and Osani with an L-shape, as a means to maximize contact to the first electrode of the second semiconductor chip (Xu, ¶ 0029), as well as minimizing module size and maximizing heat dissipation (Xu, ¶¶ 0004, 0007).
Furthermore, arriving at the claimed limitation of “the first conductive spacer in the form of an "L" shape, and disposed adjacent to an edge of the "L" shape on the electrode pattern” would have involved a mere change in the shape of a component. Absent persuasive evidence that the particular shape of the claimed conductive spacer is significant, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tsukada and Osanai as applied to claim 1 above, and further in view of Sato et al. (PG Pub. No. US 2018/0174998 A1).
Regarding claim 4, Lin in view of Tsukada and Osanai teaches the power module of claim 1, wherein the conductive spacer has a side surface (Lin, fig. 2 among others: 50 includes a side surface) that is etched to form a curved surface (not given patentable weight in a claim drawn to structure).
Lin in view of Tsukada and Osanai does not teach an area of the lower surface of the conductive spacer is formed to be larger than an area of the upper surface of the conductive spacer.
Sato teaches a conductive spacer (¶ 0029: 26) including an area of the lower surface of the conductive spacer is formed to be larger than an area of the upper surface of the conductive spacer (fig. 9 among others: lower surface of 26 larger than upper surface 26b of 26).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the conductive spacer of Lin in view of Tsukada and Osanai with a larger lower area and/or smaller upper area, as a means to provide concaves for excess bonding material, preventing overflow and contamination of surrounding areas (Sato, ¶ 0033).
Furthermore, such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In the instant case adjusting the relative size of the upper and lower conductive spacer surfaces would be a matter of routine skill, in view of Sato.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tsukada and Jeon et al. (PG Pub. No. US 2018/0102301 A1).
Regarding claim 8, Lin teaches a method for manufacturing a power module (¶ 0028: 200) comprising:
preparing a ceramic substrate (¶ 0030: substrate 180 including ceramic portion 181) by forming an electrode pattern made of a metal (¶ 0030: conductive layer 182 comprising metal) on at least one surface of a ceramic base material (fig. 2: 182 formed on at least one surface of 181), wherein the conductive spacer comprises a first conductive spacer to be bonded to a first electrode of the semiconductor chip (¶ 0025 & fig. 2: first 50 configured to bond to 31 and/or 213 of 30), and a second conductive spacer (fig. 2: 200 includes at least two conductive spacers 50) ;
preparing a conductive spacer (¶ 0025: 50);
bonding a lower surface of the conductive spacer onto the electrode pattern of the ceramic substrate (¶ 0030 & fig. 2: in an inverted orientation, lower surface of 50 at least indirectly bonded to 182), wherein a
bonding electrodes (¶ 0025: 213 or 31) of a semiconductor chip (¶¶ 0025, 0047: die 30, including devices on a semiconductor substrate) onto an upper surface of the conductive spacer (figs. 1-2: in an inverted orientation, 213/31 bonded to upper surface of 50).
Lin does not teach the second conductive spacer is configured to be bonded to a second electrode of the semiconductor chip, the first and second conductive spacers each comprise a respective plurality of conductive spacers, or the step of bonding the lower surface of the conductive spacer onto the electrode pattern of the ceramic substrate comprises brazing.
Tsukada teaches a power module (¶ 0061: 1000) including a first conductive spacer (¶ 0061: 32, similar to 50 of Lin) bonded to a first electrode (52, similar to 213 and/or 31 of Lin) of a semiconductor chip (fig. 1B: 32 bonded to 52 of semiconductor device 50, similar to 31 of Lin), and a second conductive spacer (¶ 0061: 33) bonded to a second electrode of the semiconductor chip (fig. 1B: 33 bonded to 53a of 50), the first and second conductive spacers each comprise a respective plurality of conductive spacers respectively disposed symmetrically with respect to a center point of a ceramic substrate surface (¶ 0078, fig. 1E: plurality of each 32 and 33 disposed symmetrically with respect to center point of ceramic substrate 100).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the conductive spacers of Lin with the plurality of Tsukada, as a means to provide an IPM (intelligent power module), improving functionality of the package.
Lin in view of Tsukada does not teach the step of bonding the lower surface of the conductive spacer onto the electrode pattern of the ceramic substrate comprises brazing.
Jeon teaches a method including a lower surface of a spacer (¶ 0032: 420) brazed to an electrode (¶ 0010: 620) of a ceramic substrate (¶ 0010 & fig. 5: lower surface of 420 brazed to lead 620 of ceramic substrate 220).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to perform the spacer/electrode bonding of Lin in view of Tsukada with a brazing process, as a means to enhance bonding reliability (Jeon, ¶ 0053).
Furthermore, an express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982). In the instant case, brazing is a suitable equivalent process to that of Lin for bonding spacers to electrodes, as evidenced by Jeon.
Regarding claim 10, Lin in view of Tsukada and Jeon teaches the method of claim 8, wherein in the preparing of the conductive spacer,
the conductive spacer is formed of at least one of Cu, Mo, a CuMo alloy, and a CuW alloy (Lin, ¶ 0029).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tsukada and Jeon as applied to claim 8 above, and further in view of Otremba.
Regarding claim 11, Lin in view of Tsukada and Jeon teaches the method of claim 8, comprising a conductive spacer (Lin, 50) and an electrode pattern (Lin, 182).
Lin in view of Tsukada and Jeon does not teach wherein an edge of the conductive spacer is disposed adjacent to an edge of the electrode pattern.
Otremba teaches a power semiconductor module (¶ 0003) including a conductive spacer (¶ 0040: 33) and an electrode pattern (¶¶ 0040-0042: S1, 19 and/or S2), wherein an edge of the conductive spacer is disposed adjacent to an edge of the electrode pattern (fig. 1: at least one edge of 33 adjacent to at least one edge of G1, D1, 29 and/or 39).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure an edge of the conductive spacer of Lin in view of Tsukada and Jeon adjacent to an edge of the electrode pattern, as a means to optimize contact area between the conductive spacer and the electrode pattern, enhancing thermal and/or electrical conduction (Otremba, ¶ 0035).
Furthermore, such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Response to Arguments
Applicant’s arguments with respect to the 35 USC § 103 rejections of claims 1-8 and 10-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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