DETAILED ACTION
This Office action is in response to the amendment filed 16 December 2025. By this amendment, claims 1, 4, 5, and 10 are amended. Claims 1-14 are currently pending; claims 11-14 stand withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 16 December 2026 have been fully considered but they are not persuasive; the rejections of the claims have been modified in response to Applicant’s amendments to the claims. The amended limitations (and Applicant’s arguments regarding the amended limitations) are addressed by the modified rejections below.
Claim Objections
Claim 10 is objected to because of the following informalities: due to the claim amendment, “a silicon substrate” (line 3) appears unrelated to the “semiconductor substrate” (line 3) as the claim is currently drafted. It appears the recited “silicon substrate” was intended to narrow the recited “semiconductor substrate” (e.g., wherein the semiconductor substrate is a silicon substrate) and has been interpreted for the purposes of examination as such; appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0121722 A1 to Takashima et al. (hereinafter “Takashima”) in view of WO 2018/086114 A1 (citations refer to copy submitted with the 18 October 2023 IDS; hereinafter “BOE”) and US 2023/0352910 A1 to Hamaguchi et al. (hereinafter “Hamaguchi”).
Regarding independent claim 1, Takashima (Fig. 1) discloses a method of manufacturing an optoelectronic or photovoltaic device, comprising the following successive steps:
a) forming, by PLD deposition (¶ 0088), an active layer 3 (¶¶ 0086, 92) comprising a perovskite material on the upper side of a first charge transport layer 2 (¶¶ 0086, 92; Fig. 1);
b) depositing, by PLD (¶ 0088), a second charge-transport layer 4 (¶¶ 0086, 92) of an inorganic material on the upper face of the active layer 3 (Fig. 1),
wherein steps a) and b) are carried out in a vacuum, i.e. at a pressure below atmospheric pressure (¶¶ 0088, 92).
Takashima discloses steps a) and b) are carried out at the same pressure (¶ 0092 - 700 mTorr), however fails to expressly disclose: the method including no vacuum break between steps a) and b). In the same field of endeavor, BOE (Fig. 2) discloses the PLD technique is conventionally carried out in a chamber capable of accommodating a plurality of target materials (Fig. 2; ¶¶ 0038-39). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry out the method of Takashima in a PLD chamber with target sources for the active layer and second charge-transport layer, thus enabling the execution of steps a) and b) with no vacuum break between steps a) and b), for the purpose of increasing efficiency of the manufacturing process and to reduce the risk of contamination.
Takashima also fails to expressly disclose: the active layer is a stack of multiple quantum wells consisting of alternating quantum well layers of said perovskite material and barrier layers of another semiconductor material. In the same field of endeavor, Hamaguchi discloses an optoelectronic device including an active layer having a stack of multiple quantum wells (¶ 0100) consisting of alternating quantum well layers of perovskite material (¶ 0102) and barrier layers of another semiconductor material (¶¶ 0100-02- disclosing various semiconductor materials can be used in barrier layers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an active layer as disclosed in Hamaguchi for the purpose of providing an alternative light emitting active layer structure known to be suitable for use in optoelectronic devices.
Regarding claim 2, Takashima, BOE, and Hamaguchi disclose the method of claim 1, Takashima (Fig. 1) discloses further wherein the first charge transport layer 2 is deposited by PLD prior to step a) (¶¶ 0088, 92).
Regarding claim 3, Takashima, BOE, and Hamaguchi disclose the method of claim 2, wherein the step of depositing the first charge transport layer 2 and step a) are carried out under vacuum, i.e. at a pressure lower than atmospheric pressure (¶ 0092). Takashima, BOE, and Hamaguchi fail to expressly disclose: including no vacuum break between these two steps. In view of the teachings of BOE above (see claim 1), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include no vacuum break between depositing the first charge transport layer and step a) for the purpose of increasing efficiency of the manufacturing process and to reduce the risk of contamination.
Regarding claim 4, Takashima, BOE, and Hamaguchi disclose the method of claim 2, further comprising, prior to deposition of the first charge transport layer 2, a step of depositing a lower electrode 1 (1 is used as a substrate for deposition of 2, thus is placed in the PLD apparatus chamber in a “step of depositing” as recited in the claim), the first charge transport layer 2 being deposited on the upper face of the lower electrode 1 (Takashima, Fig. 1).
Takashima, BOE, and Hamaguchi fail to expressly disclose: PLD deposition of the lower electrode. However, one of ordinary skill in the art would appreciate the lower electrode may also be formed using PLD deposition (Takashima, ¶¶ 0087-88), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the lower electrode using PLD deposition for the purpose of increasing versatility of the manufacturing process, e.g., allowing the device to be formed on different substrates or at different stages of the manufacturing process.
Regarding claim 5, Takashima, BOE, and Hamaguchi disclose the method of claim 1, Takashima (Fig. 1) discloses further comprising, after step b), a step of depositing a top electrode 6 (¶ 0094), by PLD deposition (¶¶ 0086, 94), on the top face of the second charge transport layer 4 (Fig. 1).
Regarding claim 6, Takashima, BOE, and Hamaguchi disclose the method of claim 5, in which the top electrode 6 is made of a transparent conductive material (¶ 0094 - ITO).
Regarding claim 7, Takashima, BOE, and Hamaguchi disclose the method of claim 1, Takashima discloses wherein the second charge-transport layer 4 is made of titanium dioxide, tin dioxide, nickel oxide or copper oxide (¶ 0092).
Regarding claim 8, Takashima, BOE, and Hamaguchi disclose the method of claim 1, Takashima discloses wherein the perovskite material of the active layer 3 is an inorganic perovskite material (¶ 0092).
Regarding claim 9, Takashima, BOE, and Hamaguchi disclose the method of claim 8, however fail to expressly disclose the perovskite material of the active layer is an inorganic halogen perovskite material. BOE discloses the use of inorganic halogen perovskite material in the active layer of an optoelectronic or photovoltaic device (¶ 0030). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the material of BOE, inorganic halogen perovskite material, in the active layer of Takashima, BOE, and Hamaguchi for the purpose of utilizing an art recognized material known to be suitable for use in active layers and to provide a material with high carrier mobility (BOE, ¶ 0028).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Takashima, BOE, and Hamaguchi as applied to claim 1 above, and further in view of US 2003/0021732 A1 to Tungare et al. (hereinafter “Tungare”).
Regarding claim 10, as best understood, Takashima, BOE, and Hamaguchi disclose the method of claim 1, however fail to expressly disclose: wherein, prior to step a), the first charge transport layer is deposited on the top surface of an integrated circuit previously formed in and on a semiconductor substrate, a silicon substrate. Utilizing PLD to form optoelectronic or photovoltaic devices in integrated circuits formed in and on semiconductor substrates, including silicon substrates, is well-known in the art and conventional practice for forming systems of devices having a desired function (see, e.g., Tungare, Fig. 24, ¶ 0064).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the device on the top surface of an integrated circuit previously formed in and on a semiconductor substrate, thus disclosing a method wherein prior to step a), the first change transport layer is deposited on the top surface of an integrated circuit previously formed in and on a semiconductor substrate, because including optoelectronic or photovoltaic devices in integrated circuits formed in and on semiconductor substrates is conventional practice in the art in order to form systems having a desired function, e.g., displays, solar cells.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CANDICE Y. CHAN
Examiner
Art Unit 2813
21 April 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights