Prosecution Insights
Last updated: July 17, 2026
Application No. 18/287,650

SEMICONDUCTOR DEVICE AND POWER CONVERSION APPARATUS

Non-Final OA §103
Filed
Oct 20, 2023
Priority
May 27, 2021 — nonprovisional of PCTJP2021020212
Examiner
LEE, ALVIN LYNGHI
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
66 granted / 74 resolved
+21.2% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
33 currently pending
Career history
120
Total Applications
across all art units

Statute-Specific Performance

§103
81.4%
+41.4% vs TC avg
§102
8.6%
-31.4% vs TC avg
§112
5.7%
-34.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 74 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Species A in the reply filed on March 27, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 5-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 27, 2026. Note to Applicant Examiner notes that Sugawara et. al. (US 20210091220 A1) constitutes prior art under 35 USC §102(a)(1). However, this reference appears to qualify as exempted under the 35 USC §102(b)(1)(a) exemption. A statement must be filed by the Applicant so this exemption is applied and a future rejection is not required. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the a depth of the second trench, a depth of the third trench, a depth of the first trench in the main cell region, and a depth of the first trench in the sense cell region are the same of claim 2 (Examiner notes there are no markers or indicators to demonstrate the same depth) a width of the mesa is equal to or less than a width between a plurality of the first trenches in the main cell region and is equal to or less than a width between a plurality of the first trenches in the sense cell region of claim 4 (Examiner notes there are no markers or indicators to demonstrate the same depth) a connection electrode that is provided on the third bottom protection layer and connected to the current sense electrode of claim 10 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-4, 8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Morino et. al. (US 2015333127 A1), hereinafter Morino, in view of Kagawa et. al. (US 20150357415 A1), hereinafter Kagawa. Regarding claim 1, Morino teaches a semiconductor device (Fig 1 not labeled SiC semiconductor device, [0038]) comprising: a main cell region (Fig 1 main cell region Rm, [0038]) and a sense cell region (Fig 1 sense cell region Rs, [0038]) that are separated from each other (Fig 1); a first peripheral region (See annotated figure) that is adjacent to the main cell region (Fig 1 main cell region Rm, [0038]) between the main cell region (Fig 1 main cell region Rm, [0038]) and the sense cell region (Fig 1 sense cell region Rs, [0038]); a second peripheral region (See annotated figure) that is adjacent to the sense cell region (Fig 1 sense cell region Rs, [0038]) between the main cell region (Fig 1 main cell region Rm, [0038]) and the sense cell region (Fig 1 sense cell region Rs, [0038]); and a separation region (See annotated figure) that separates the first peripheral region (See annotated figure) and the second peripheral region (See annotated figure) from each other, wherein the main cell region (Fig 1 main cell region Rm, [0038]), the first peripheral region (See annotated figure), the separation region (See annotated figure), the second peripheral region (See annotated figure), and the sense cell region (Fig 1 sense cell region Rs, [0038]) include a drift layer (Fig 1 drift layer 2, [0039]) of a first conductivity type (n-type, [0039]), each of the main cell region (Fig 1 main cell region Rm, [0038]) and the sense cell region (Fig 1 sense cell region Rs, [0038]) further includes a body region (Fig 1 base region 3, [0039]) of a second conductivity type (p-type, [0039]) that is provided on (Fig 1) the drift layer (Fig 1 drift layer 2, [0039]), a source region (Fig 1 source region 4, [0039]) of the first conductivity type (n-type, [0039]) that is provided on (Fig 1) the body region (Fig 1 base region 3, [0039]), a first trench (Fig 1 trench 6, [0040]) that penetrates the body region (Fig 1 base region 3, [0039]) and the source region (Fig 1 source region 4, [0039]) and is partially in contact with the drift layer (Fig 1 drift layer 2, [0039]), a gate electrode (Fig 1 gate electrode 8, [0041]) that is provided in (Fig 1) the first trench (Fig 1 trench 6, [0040]) via a gate insulating film (Fig 1 gate insulating film 7, [0041]), the main cell region (Fig 1 main cell region Rm, [0038]) further includes a source electrode (Fig 1 source electrode 10 in main cell region Rm, [0044]) that is connected to (Fig 1) the source region (Fig 1 source region 4, [0039]), the sense cell region (Fig 1 sense cell region Rs, [0038]) further includes a current sense electrode (Fig 1 source electrode 10 in sense cell region Rs, [0044]) that is connected to (Fig 1) the source region (Fig 1 source region 4, [0039]) and separate from (Fig 1) the source electrode (Fig 1 source electrode 10 in main cell region Rm, [0044]), the first peripheral region (See annotated figure) further includes a second trench (See annotated figure) that is provided above (Fig 1) the drift layer (Fig 1 drift layer 2, [0039]) and is wider than (See annotated figure) the first trench (Fig 1 trench 6, [0040]); and a second bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the second trench) of the second conductivity type (p-type, [0039]) that is provided at the bottom of (Fig 1) the second trench (See annotated figure), the second peripheral region (See annotated figure) further includes a third trench (See annotated figure) that is provided above (Fig 1) the drift layer (Fig 1 drift layer 2, [0039]) and is wider (Fig 1) than the first trench (Fig 1 trench 6, [0040]), and a third bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the third trench) of the second conductivity type (p-type, [0039]) that is provided at the bottom of (Fig 1) the third trench (See annotated figure), and the second bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the second trench) is electrically connected (implied since the purpose is to relax the field concentration, [0047]) to the source electrode (Fig 1 source electrode 10 in main cell region Rm, [0044]), the third bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the third trench) is electrically connected (implied since the purpose is to relax the field concentration, [0047]) to the current sense electrode (Fig 1 source electrode 10 in sense cell region Rs, [0044]), or the second bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the second trench) and the third bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the third trench) are respectively electrically connected (implied since the purpose is to relax the field concentration, [0047]) to the source electrode (Fig 1 source electrode 10 in main cell region Rm, [0044]) and the current sense electrode (Fig 1 source electrode 10 in sense cell region Rs, [0044]). Morino fails to teach a first bottom protection layer of the second conductivity type that is provided at a bottom of the first trench, and a connection layer of the second conductivity type that is provided along at least a part of a sidewall of the first trench and connects the first bottom protection layer and the body region. However, Kagawa teaches a first bottom protection layer (Fig 2b protective diffusion layer 13, [0040]) of the second conductivity type (p-type, [0040] corresponds to Morino: p-type, [0039]) that is provided at a bottom of the first trench (Fig 1 trench 5 corresponds to Morino: Fig 1 trench 6, [0040]), and a connection layer (Fig 2b second base region 14, [0048]) of the second conductivity type (p-type, [0048] corresponds to Morino: p-type, [0039]) that is provided along at least a part of a sidewall (Fig 2b, [0048]) of the first trench (Fig 1 trench 5 corresponds to Morino: Fig 1 trench 6, [0040]) and connects the first bottom protection layer (Fig 2b protective diffusion layer 13, [0040]) and the body region (Fig 2b base region 3, [0048] corresponds to Morino: Fig 1 base region 3, [0039]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Morino to incorporate the teachings of Kagawa by having a first bottom protection layer of the second conductivity type that is provided at a bottom of the first trench and a connection layer of the second conductivity type that is provided along at least a part of a sidewall of the first trench and connects the first bottom protection layer and the body region. The bottom protection layer being used for improving device performance ([0040]). The connection layer being used to electrically connect the bottom protection layer to the base region in order to prevent the protective diffusion layer from being electrically floating ([0049]). PNG media_image1.png 876 814 media_image1.png Greyscale Regarding claim 3, Morino as modified in claim 1 teaches a mesa (See annotated figure) that electrically separates the second bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the second trench) from the third bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the third trench) is provided in the separation region (See annotated figure). PNG media_image2.png 876 814 media_image2.png Greyscale Regarding claim 4, Morino as modified in claim 3 fails to teach a width of the mesa is equal to or less than a width between a plurality of the first trenches (Fig 1 trench 6, [0040]) in the main cell region (Fig 1 main cell region Rm, [0038]) and is equal to or less than a width between a plurality of the first trenches (Fig 1 trench 6, [0040]) in the sense cell region (Fig 1 sense cell region Rs, [0038]). However, Morino teaches a width of an isolation portion between field relaxation layers Wp is set such that the field relaxation layers will be sufficiently isolated from each other in their respective main cell and sense cell regions ([0073]). Further, one having ordinary skill in the art before the effective filing date of the claimed invention would want the greatest number of cells in both the main cell region and sense region. In addition, Morino teaches there is a predetermined ratio of cells in the main cell region and sense cell region ([0053]). The relationship between the width of the mesa and between trenches is therefore a result-effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width of the mesa and the width between trenches as Morino has identified the relationship between the widths as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a width of the mesa is equal to or less than a width between a plurality of the first trenches in the main cell region and is equal to or less than a width between a plurality of the first trenches in the sense cell region, in order to achieve the desired balance between the width of the isolation portion and the number of cells in the main cell and sese region, as taught by Morino. MPEP 2144.05. Furthermore, the applicant has not presented persuasive evidence that the claimed relationship of widths is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions). Regarding claim 8, Morino as modified in claim 1 teaches a well contact layer (Fig 1 contact region 5, [0063]) that is provided on the body region (Fig 1 base region 3, [0039]) in the sense cell region (Fig 1 sense cell region Rs, [0038]) and has an impurity concentration of the second conductivity type (p-type, [0039]) higher than (p+, [0063]; Examiner notes that one having ordinary skill in the art before the effective filing date of the claimed invention would p+ would indicate a higher concentration than p) an impurity concentration of the body region (Fig 1 base region 3, [0039]), wherein in any cross section, both ends of the (See annotated figure) well contact layer (Fig 1 contact region 5, [0063]) are located outside both ends (See annotated figure) of a contact hole (See annotated figure) adjacent to (See annotated figure) the well contact layer (Fig 1 contact region 5, [0063]). PNG media_image3.png 836 840 media_image3.png Greyscale Regarding claim 11, Morino as modified in claim 1 teaches the drift layer (Fig 1 drift layer 2, [0039]) includes a wide band gap semiconductor (SiC, [0039]). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Morino et. al. (US2015333127A1), hereinafter Morino, in view of Kagawa et. al. (US 20150357415 A1), hereinafter Kagawa., in further view of Okumura (US 20190189756 A1). Morino as modified in claim 1 fails to teach a depth of the second trench (See annotated figure), a depth of the third trench (See annotated figure), a depth of the first trench (Fig 1 trench 6, [0040]) in the main cell region (Fig 1 main cell region Rm, [0038]), and a depth of the first trench (Fig 1 trench 6, [0040]) in the sense cell region (Fig 1 sense cell region Rs, [0038]) are the same. Regarding the depths of the trenches, the process to get the depths would have been obvious to try. Morino teaches the depths of the trenches as different (Fig 1). Okumura teaches gate trenches (Fig 16 gate trenches 9, [0079] correspond to Morino: Fig 1 trench 6, [0040]) and isolation trenches (Fig 16 isolation trench 9a corresponds to Morino: second and third trench from annotated figure of claim 1) are formed at the same time. This would reduce manufacturing steps since the different trenches are formed at the same time. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that trenches would be formed either through multiple steps or a single step, with the single step method reducing the manufacturing time. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421. In applying the teachings of Okumura to Morino as modified in claim 1, a depth of the second trench (See annotated figure), a depth of the third trench (See annotated figure), a depth of the first trench (Fig 1 trench 6, [0040]) in the main cell region (Fig 1 main cell region Rm, [0038]), and a depth of the first trench (Fig 1 trench 6, [0040]) in the sense cell region (Fig 1 sense cell region Rs, [0038]) would all be the same. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Morino et. al. (US2015333127A1), hereinafter Morino, in view of Kagawa et. al. (US 20150357415 A1), hereinafter Kagawa., in further view of Kumada et. al. (US 20150270387 A1), hereinafter Kumada. Morino as modified in claim 1 fails to teach a capacitance electrode that is provided on the third bottom protection layer with an insulating film interposed therebetween, wherein the capacitance electrode is connected to the gate electrode in the sense cell region. However, Kumada teaches a capacitance electrode (Fig 11 planar gate electrode 60, [0065]) that is provided on a well region (Fig 11 well region 32, [0064]) in a drift layer (Fig 11 drift layer 1, [0064]) with an insulating film (Fig 11 insulating film 61, [0064]) interposed therebetween in a separating structure (Fig 11 separating structure 62, [0064])m wherein the capacitance electrode is connected to the gate electrode of trench gates ([0065]). The capacitance electrode allows the potential of the front surface of the well region to approach that of the gate electrode ([0065]). One having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to combine variations of capacitance electrodes and insulating film with each element performing the same function as it does separately and the result from the combination of the different structures would have been predictable. Thus, by combining the different capacitance electrodes and insulating film structures with variations in the third bottom protection layer the structure of the claimed invention would be realized. MPEP 2143(I)(G) Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Morino et. al. (US2015333127A1), hereinafter Morino, in view of Kagawa et. al. (US 20150357415 A1), hereinafter Kagawa., in further view of Kensuke et. al. (WO 2017010164 A1), hereinafter Kensuke. Morino as modified in claim 1 fails to teach a connection electrode that is provided on the third bottom protection layer (Fig 1 relaxation layer 15 at the bottom of the third trench) and connected to the current sense electrode (Fig 1 source electrode 10 in sense cell region Rs, [0044]). However, Fukui teaches a connection electrode (Fig 1 Schottky electrode 34, second to last paragraph on page 15 of translation) that is provided on the third bottom protection layer (Fig 1 protective diffusion region 14, second to last paragraph on page 15 of translation) and connected to a source electrode (Fig 1 source electrode 32, last paragraph on page 15 of translation). This helps to reduce the ohmic resistance between the protective diffusion region and the source electrode (second to last paragraph on page 15 of translation). One having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to combine variations of connection electrodes and protection layers with each element performing the same function as it does separately and the result from the combination of the different structures would have been predictable. Thus, by combining the different connection electrodes variations in the third bottom protection layer the structure of the claimed invention would be realized. MPEP 2143(I)(G) Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Morino et. al. (US2015333127A1), hereinafter Morino, in view of Kagawa et. al. (US 20150357415 A1), hereinafter Kagawa., in further view of Adachi et. al. (US 20190206987 A1), hereinafter Adachi. Morino as modified in claim 1 fails to teach a power conversion apparatus comprising: a main conversion circuit that includes the semiconductor device according to claim 1 and converts and outputs input power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. However, Adachi teaches a power conversion apparatus (Fig 35 power conversion device 600, [0164]) comprising: a main conversion circuit (Fig 35 main conversion circuit 601, [0165]) that includes the semiconductor device according to claim 1 (Fig 35 not shown switching element, [0167] corresponds to Morino: Fig 1 not labeled SiC semiconductor device, [0038]) and converts and outputs ([0167]) input power (Fig 35 power supply 500, [0167]); a drive circuit (Fig 35 drive circuit 602, [0168]) that outputs a drive signal ([0168]) for driving the semiconductor device (Fig 35 not shown switching element, [0167] corresponds to Morino: Fig 1 not labeled SiC semiconductor device, [0038]) to the semiconductor device (Fig 35 not shown switching element, [0167] corresponds to Morino: Fig 1 not labeled SiC semiconductor device, [0038]); and a control circuit (Fig 35 control circuit 603, [0169]) that outputs a control signal ([0169]) for controlling the drive circuit (Fig 35 drive circuit 602, [0168]) to the drive circuit (Fig 35 drive circuit 602, [0168]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Morino and Kagawa to incorporate the teachings of Adachi by implementing the semiconductor device in a power conversion apparatus. This would provide a use case. Conclusion The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALVIN L LEE/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Oct 20, 2023
Application Filed
Apr 27, 2026
Non-Final Rejection mailed — §103
Jun 11, 2026
Interview Requested
Jul 07, 2026
Examiner Interview Summary
Jul 07, 2026
Applicant Interview (Telephonic)

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.4%)
3y 2m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 74 resolved cases by this examiner. Grant probability derived from career allowance rate.

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