DETAILED ACTIONNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harada et al (JP2019047046) (herein “Harada”) (Copy supplied by Applicant). In regards to claim 1, Harada teaches a semiconductor device comprising: a first cell array (See; Fig. 3 MU circuits in AC[1]), a second cell array (See; Fig. 3 MU circuits in AC[2]), and a first converter circuit (See; Fig. 3 for OU circuits in AC[1]), wherein the first cell array comprises a first cell and a second cell positioned in the same row as the first cell, wherein the second cell array comprises a third cell and a fourth cell positioned in the same row as the third cell, wherein the first converter circuit comprises a plurality of input terminals and a plurality of output terminals (See; Fig. 3), wherein the first cell is electrically connected to a first wiring and a second wiring, wherein the second cell is electrically connected to the first wiring and a third wiring, wherein each of the plurality of input terminals of the first converter circuit is electrically connected to the second wiring and the third wiring (See; Fig. 3 where the input terminals of the OU circuits in AC[1] connect to the second and third wiring running to the MU circuits), wherein each of the plurality of output terminals of the first converter circuit is electrically connected to a fourth wiring and a fifth wiring, wherein the third cell is electrically connected to the fourth wiring and a sixth wiring, wherein the fourth cell is electrically connected to the fifth wiring and a seventh wiring (See; Fig. 3 where the output terminals of the OU circuits in AC[1] connect to the fourth and fifth wiring running to the MU circuits in AC[2]), wherein the first cell is configured to make a first current with an amount corresponding to a product of a first data retained in the first cell and a second data input from the first wiring to the first cell flow to the second wiring (See; p[0040] and p[0091]-p[0148] where the MU circuits perform a product-sum operation), wherein the second cell is configured to make a second current with an amount corresponding to a product of a third data retained in the second cell and a fourth data input from the first wiring to the second cell flow to the third wiring (See; p[0040] and p[0091]-p[0148] where the MU circuits perform a product-sum operation), wherein the first converter circuit is configured to make a fifth data corresponding to a total amount of current flowing from the second wiring flow to the fourth wiring and is configured to make a function of making a sixth data corresponding to a total amount of current flowing from the third wiring flow to the fifth wiring (See; p[0040] and p[0091]-p[0148] where the OU circuit has a function of converting the amount of current flowing from wiring inputting from AC[1}), wherein the third cell is configured to make a third current with an amount corresponding to a product of a seventh data retained in the third cell and the fifth data input from the fourth wiring to the third cell flow to the sixth wiring(See; p[0040] and p[0091]-p[0148] where the MU circuits in AC[2] perform a product-sum operation), wherein the fourth cell is configured to make a fourth current with an amount corresponding to a product of an eighth data retained in the fourth cell and the sixth data input from the fifth wiring to the fourth cell flow to the seventh wiring, and wherein the sixth wiring is electrically connected to the seventh wiring (See; p[0040] and p[0091]-p[0148] where the MU circuits in AC[2] perform a product-sum operation). In regards to claim 2, Harada teaches a second converter circuit, wherein the second converter circuit comprises an input terminal and an output terminal, wherein the input terminal of the second converter circuit is electrically connected to the sixth wiring, and wherein the second converter circuit is configured to output a ninth data corresponding to a total amount of current flowing from the sixth wiring to the output terminal of the second converter circuit (See; Fig. 3 for OU circuits in AC[2]). In regards to claim 3, Harada teaches a fifth cell, a sixth cell, and a seventh cell (See; Fig. 3), wherein the first cell, the second cell, the third cell, and the fourth cell each include a first transistor, a second transistor, and a first capacitor (See; Fig. 6(B) for a first transistor Tr1, second transistor Tr2 and a capacitor C1 in each MU), wherein the fifth cell, the sixth cell, and the seventh cell each include a third transistor, a fourth transistor, and a second capacitor (See; Fig. 6(B) for a first transistor Tr1, second transistor Tr2 and a capacitor C1 in each MU,) wherein in each of the first cell, the second cell, the third cell, and the fourth cell, a gate of the first transistor is electrically connected to a first terminal of the first capacitor and a first terminal of the second transistor (See; Fig. 6(B)), wherein, in each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a second terminal of the second transistor, wherein, in the first cell, the first terminal of the first transistor is electrically connected to the second wiring (See; Fig. 6(B)), wherein, in the first cell, a second terminal of the first capacitor is electrically connected to the first wiring, wherein, in the second cell, the first terminal of the first transistor is electrically connected to the third wiring, wherein, in the second cell, a second terminal of the first capacitor is electrically connected to the first wiring, wherein, in the third cell, the first terminal of the first transistor is electrically connected to the sixth wiring, wherein, in the third cell, a second terminal of the first capacitor is electrically connected to the fourth wiring, wherein, in the fourth cell, the first terminal of the first transistor is electrically connected to the seventh wiring, wherein, in the fourth cell, a second terminal of the first capacitor is electrically connected to the fifth wiring, wherein, in each of the fifth cell, the sixth cell, and the seventh cell, a gate of the third transistor is electrically connected to a first terminal of the second capacitor and a first terminal of the fourth transistor, wherein, in each of the fifth cell, the sixth cell, and the seventh cell, a first terminal of the third transistor is electrically connected to a second terminal of the fourth transistor, wherein, in the fifth cell, the first terminal of the third transistor is electrically connected to the first wiring, wherein, in the fifth cell, a second terminal of the second capacitor is electrically connected to the first wiring, wherein, in the sixth cell, the first terminal of the third transistor is electrically connected to the fourth wiring, wherein, in the sixth cell, a second terminal of the second capacitor is electrically connected to the fourth wiring, wherein, in the seventh cell, the first terminal of the third transistor is electrically connected to the fifth wiring, and wherein, in the seventh cell, a second terminal of the second capacitor is electrically connected to the fifth wiring (See; Fig. 3, 6(B) where all MU cells mentioned above are wired the same based on their position in the array or within AC[1] or Ac[2] and would read on the above wiring configurations). In regards to claim 4, Harada teaches a first circuit and a second circuit, wherein the first circuit is electrically connected to the first wiring, wherein the second circuit is electrically connected to the fourth wiring and the fifth wiring, wherein the first circuit is configured to input has a function of inputting the second data to the first wiring (See; Fig. 3 for gate driver 12), and wherein the second circuit is configured to make has a function of making current flow to the fourth wiring and the fifth wiring (See; Fig. 3 for OU circuits in AC[1]).
In regards to claim 5, Harada teaches display apparatus comprising: a first layer comprising the semiconductor device according to any one of claim 1 and a second layer comprising a display portion, wherein the second layer comprises a region overlapping with the first layer (See; Figs. 12 and 13 for a layering arrangement of the arithmetic circuit and display).
In regards to claim 6, Harada teaches an electronic device comprising the display apparatus according to claim 5 and a housing (See; Figs. 14-16 for various implementations of a display and a housing of an electronic device).
Conclusion
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/JONATHAN A BOYD/Primary Examiner, Art Unit 2627