DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/30/2024 and 07/03/2025 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation "the transistor" in line 6. There is insufficient antecedent basis for this limitation in the claim. NOTE: the Applicant previously claims a plurality of transistors in line 5 instead of a transistor. Thereof, the Examiner suggests to amend wherein each transistor of the plurality of transistors to be sufficient antecedent basis for the limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 22 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Du (WO 2021/184274 A1).
Regarding claim 1, Du teaches a display substrate (see figs. 1-3), comprising:
a base substrate (refer to 010 in fig. 1),
a plurality of sub-pixels (refer to spx in fig. 1), located on the base substrate (refer to 010), wherein each of the plurality of sub-pixels (refer to 0121 in fig. 2) comprises a light-emitting element (refer to 0120 or LED) and a pixel circuit (refer to 0121), the pixel circuit (refer to 0121) is configured to drive the light-emitting element (refer to 0120), the pixel circuit (refer to 0121) comprises a plurality of transistors (refer to T1…T7) and a storage capacitor (refer to CST), each of the plurality of transistors comprises a gate electrode (refer to gate electrode of T1…T7), a first electrode (refer to source/drain electrode of T1…T7), and a second electrode (refer to drain/source electrode of T1…T7);
a plurality of signal lines (refer to VINIT1/VINIT2/GA1/GA2/EM/VD), arranged on the base substrate (refer to 010), comprising a first initialization signal line (refer to VINIT1), a reset control signal line (GA1), and a second initialization signal line (refer to VINIT2) which extend in a first direction (refer to vertical direction or known as y-axis) and are arranged in a second direction (refer to horizontal direction or known as x-axis), wherein the reset control signal line (GA1) is configured to supply a reset control signal to the pixel circuit, the first initialization signal line (refer to VINIT1) is configured to supply a first initialization signal to the pixel circuit, and the second initialization signal line (refer to VINIT2) is configured to supply a second initialization signal to the pixel circuit, the second direction intersects with the first direction,
wherein the plurality of transistors comprise a first reset transistor (refer to T6) and a second reset transistor (refer to T7), a first electrode of the first reset transistor (refer to source/drain electrode of T6) is electrically connected with the first initialization signal line (refer to VINIT1), and a gate electrode of the first reset transistor (refer to gate electrode of T6) and a gate electrode of the second reset transistor (refer to gate electrode of T7) are electrically connected with the reset control signal line (refer to GA1), a first electrode of the second reset transistor (refer to source/drain electrode of T7) is electrically connected with the second initialization signal line (refer to VINIT2), and a second electrode of the second reset transistor (refer to drain/source of T7) is electrically connected with the light-emitting element (refer to 0120),
an orthographic projection of at least one of the first initialization signal line and the second initialization signal line on the base substrate does not overlap with an orthographic projection of the reset control signal line on the base substrate (see fig. 3).
Regarding claim 22, Du teaches a display substrate in figs. 1-3, comprising:
a base substrate (refer to 010) (see fig. 1);
a plurality of sub-pixels (refer to spx in fig. 1), located on the base substrate (010), wherein each of the plurality of sub-pixels (refer to 0121 in fig. 2) comprises a light-emitting element (0120) and a pixel circuit (refer to 0121 in fig. 2), the pixel circuit (refer to 0121) is configured to drive the light-emitting element (refer to 0120 in fig. 2), the pixel circuit comprises a plurality of transistors (refer to T1/T2/T3/T4/T5/T6/T7 in fig. 5) and a storage capacitor (refer to CST), the transistor (refer to T1/T2/T3/T4/T5/T6/T7) comprises a gate electrode (refer to gate electrode of each transistor T1…T7), a first electrode (refer to source/drain electrode of each transistor T1…T7), and a second electrode (refer to drain/source of each transistor T1…T7);
a plurality of signal lines (refer to VINIT1/GA1/GA2/EM/VD/ VINIT2), arranged on the base substrate, comprising an initialization signal line (VINIT1) and a reset control signal line (GA1), wherein the initialization signal line (refer to VINIT1 in fig. 2) is configured to supply an initialization signal to the pixel circuit, and the reset control signal line (refer to GA1 in fig. 2) is configured to supply a reset control signal to the pixel circuit;
wherein the plurality of transistors comprise a reset transistor (T6/T7), a gate electrode of the reset transistor (refer to gate electrode of T6 or T7) is connected with the reset control signal line (refer to GA1), a first electrode of the reset transistor (refer to source/drain electrode of T6 or T7) is connected with the initialization signal line (GA1), and the reset transistor is configured to reset a first electrode of the storage capacitor (refer to CST) or a first electrode of the light-emitting element (refer to 0120),
an orthographic projection of the initialization signal line (refer to VINIT1) on the base substrate does not overlap with an orthographic projection of the reset control signal line (refer to GA1) on the base substrate (see fig. 3).
Regarding claim 27, Du teaches a display device in fig. 1 comprising: the display substrate according to claim 1 (see claim 1’s above explanation).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Du (WO 2021/184274 A1).
Regarding claim 24, Du teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 2 of Du teaches the reset transistor (refer to 0129) comprises a second reset transistor (T7), the initialization signal line comprises a second initialization signal line (refer to VINIT2), the second reset transistor (refer to T7) is configured to reset the first electrode of the light-emitting element (refer to 0120).
Fig. 2 of Du shows the first initialization signal line and the second initialization signal line are extending on the vertical direction and arranged in a horizontal direction and fig. 3 of Du shows an orthographic projection of the first initialization signal line on the base substrate does not overlap with the orthographic projection of the reset control signal line on the base substrate.
Thus, it would be obvious to one having ordinary skills in the art before the invention was made to include an orthographic projection of the second initialization signal line on the base substrate does not overlap with the orthographic projection of the reset control signal line on the base substrate in teaching of Du order to simply the design of the display substrate by having the second initialization signal line on the base substrate as the same design as the first initialization signal line on the base substrate as shown in fig. 3 of Du.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the plurality of transistors further comprise a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor, and the plurality of signal lines further comprise a light-emitting control signal line, the light-emitting control signal line extends in the first direction, a first electrode of the first light-emitting control transistor is electrically connected with a second electrode of the storage capacitor, a first electrode of the second light-emitting control transistor is electrically connected with the second electrode of the second reset transistor, and a gate electrode of the first light-emitting control transistor and a gate electrode of the second light-emitting control transistor are electrically connected with the light-emitting control signal line, and a second electrode of the second light-emitting control transistor and a second electrode of the first light-emitting control transistor are connected with a first electrode and a second electrode of the driving transistor, respectively, and a gate electrode of the driving transistor is connected with a first electrode of the storage capacitor, an orthographic projection of the first initialization signal line on the base substrate at least partially overlaps with an orthographic projection of the light-emitting control signal line on the base substrate.” Claims 9-10,12-13 includes all the limitations of claim 2.
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “wherein the plurality of transistors further comprise a refresh control transistor, a first electrode of the refresh control transistor is electrically connected with a first electrode of the storage capacitor, a second electrode of the refresh control transistor is electrically connected with a second electrode of the first reset transistor, the plurality of signal lines further comprise a refresh gate line, the refresh gate line extends in the first direction, a gate electrode of the refresh control transistor is electrically connected with the refresh gate line, and the orthographic projection of the second initialization signal line on the base substrate at least partially overlaps with an orthographic projection of the refresh gate line on the base substrate.” Claims 6, 16-18, 20 include all the limitations of claim 3.
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “wherein the first initialization signal line and the second initialization signal line are arranged to be spaced apart in the second direction.”
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “wherein in the second direction, the first initialization signal line is located between the first electrode of the first reset transistor and the storage capacitor, and the orthographic projection of the first initialization signal line on the base substrate does not overlap with an orthographic projection of the storage capacitor on the base substrate.”
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the reset transistor comprises a first reset transistor, the initialization signal line comprises a first initialization signal line, and the first reset transistor is configured to reset the first electrode of the storage capacitor, an orthographic projection of the first initialization signal line on the base substrate does not overlap with the orthographic projection of the reset control signal line on the base substrate.”
Claim 25 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “wherein the plurality of transistors further comprise a refresh control transistor, a first electrode of the refresh control transistor is electrically connected with the first electrode of the storage capacitor, and a second electrode of the refresh control transistor is connected with a second electrode of the first reset transistor, the plurality of signal lines further comprise a refresh gate line, the refresh gate line extends in a first direction, and a gate electrode of the refresh control transistor is electrically connected with the refresh gate line; the orthographic projection of the second initialization signal line on the base substrate at least partially overlaps with an orthographic projection of the refresh gate line on the base substrate.”
Claim 26 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “wherein the plurality of transistors further comprise a driving transistor and a light-emitting control transistor, and the plurality of signal lines further comprise a light-emitting control signal line, and the light-emitting control signal line extends in a first direction, a first electrode of the light-emitting control transistor is electrically connected with a second electrode of the second reset transistor, a gate electrode of the light-emitting control transistor is electrically connected with the light-emitting control signal line, and a second electrode of the light-emitting control transistor is connected with the driving transistor, the orthographic projection of the first initialization signal line on the base substrate at least partially overlaps with an orthographic projection of the light-emitting control signal line on the base substrate.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818