Prosecution Insights
Last updated: April 19, 2026
Application No. 18/288,999

SEMICONDUCTOR DEVICE AND POWER CONVERTER

Non-Final OA §102§103
Filed
Oct 31, 2023
Examiner
WARREN, MATTHEW E
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
862 granted / 986 resolved
+19.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
1011
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 986 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the Preliminary Amendment filed on October 31, 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, and 8, 10, 12, and 13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Nakajima (JP 2014022444 A). In re claim 1, Nakajima shows (figs. 1-1, 1-2, 1-3, 1-5) semiconductor device comprising: a lead frame (1) having a mount surface; a semiconductor element (4) disposed on the mount surface; a circuit board (5) disposed apart from the mount surface in a thickness direction of the semiconductor device and electrically connected to the lead frame (by 6c); a sealing resin (7) to seal the lead frame, the semiconductor element, and the circuit board; a connector (part of 5a) having a terminal portion, wherein the lead frame includes a lead (1b) exposed from the sealing resin, the circuit board (5) has at least one exposed portion (5a) exposed from the sealing resin, and the terminal portion (5a) of the connector is exposed from the sealing resin electrically connected to one of the at least one exposed portion (since 5a is considered the terminal portion is also the exposed portion. In re claim 8, Nakajima shows (figs. 1-1, 1-2, 1-3, 1-5) a number of the at least one exposed portion is greater than or equal to two. In re claim 10, Nakajima shows (figs. 1-1, 1-2, 1-3, 1-5) the at least one exposed portion is inside an outline of the sealing resin when viewed along a thickness direction of the semiconductor device. In re claims 12 and 13, Nakajima shows (figs. 1-1, 1-2, 1-3, 1-5, and abstract) the connector serves as a control terminal of the semiconductor device, and the lead serves as a main circuit terminal of the semiconductor device (because the connector 5 is a control board). The device is a power converter comprising: a main conversion circuit to convert and output input power, the main conversion circuit including the semiconductor device (4) according to claim 1; and a control circuit (control board 5) to output a control signal controlling the main conversion circuit to the main conversion circuit. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nakajima (JP 2014022444 A). In re claim 2, Nakajima shows all of the elements of the claims except the thickness of the at least one exposed portion is smaller than a thickness of a portion of the circuit board sealed with the sealing resin. It would have been obvious to one of ordinary skill in the art at the time the invention was made to form the exposed portion having any desired thickness, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). In re claims 9 and 11, Nakajima shows all of the elements of the claims except the through hole or penetration hole with the screw inserted. These elements are not patentably distinguishable over the cited prior art since the are well known in the art of semiconductors for forming secure connections in electronic devices. Allowable Subject Matter Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Glenn (US 6,566,164 B1), Oka (US Pub. 2010/0133667 A1), Noritake (US Pub. 2009/0224398 A1), Shinohara (US Pub. 2006/0091512 A1), Mashimo (US Pub. 2012.0074552 A1), Ishihara (JP-2006054245 A), and Yamaguchi (CN-113316845 B) also disclose various elements of the claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Oct 31, 2023
Application Filed
Jan 10, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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INTEGRATED PASSIVE DEVICE DIES AND METHODS OF FORMING AND PLACEMENT OF THE SAME
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PHOTO DIODE WITH DUAL BACKSIDE DEEP TRENCH ISOLATION DEPTH
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Patent 12593455
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12593453
FERROELECTRIC MEMORY DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12588271
MULTI-LAYER ELECTRODE TO IMPROVE PERFORMANCE OF FERROELECTRIC MEMORY DEVICE
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+5.6%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 986 resolved cases by this examiner. Grant probability derived from career allow rate.

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