DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s cancellation of claim 12 overcomes the previous drawings objection.
Applicant's arguments filed 06/18/2026 have been fully considered but they are only partially persuasive as they overcome the previously applied Hara reference but fail to overcome the previously applied Suzuki reference. Specifically, Applicant argues on pages 7 and 8 that Suzuki teaches wherein portions of the lower gate wiring line GL1 and the upper gate wiring line GL2, intersecting the oxide semiconductor layer 7 can function as the lower gate electrode GE1 and the upper gate electrode GE2 of the corresponding TFT 20, and that therefore Applicant’s identified regions of Suzuki fail to teach the language of amended claim 1 of “wherein an orthographic projection of the connection portion on the substrate is located within an orthographic projection of the second gate on the substrate”. However, Applicant’s identification of a portion as the second gate in Suzuki is inconsistent with the use of the term “second gate” in Applicant’s disclosure since Applicant identifies the entire line 105 extending in the X direction as the second gate:
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[0073] Referring to FIG. 4, in some embodiments, a connection 138 is provided between the first gates 104 of at least two of the first thin film transistors 103 in the first direction X, and the connection 138 connects the first gates 104 of the two first thin film transistors 103. The orthographic projection of the connection portion 138 on the substrate 101 is located in the orthographic projection of the second gate electrode 105 on the substrate 101, so as to reduce shielding of light by the connection portion 138, thereby facilitating increasing the aperture ratio of the display panel to which the array substrate 100 is applied. When the orthographic projection of the connection portion 138 on the substrate 101 is located in the orthographic projection of the second gate electrode 105 on the substrate 101, the width of the connection portion 138 in the second direction Y is smaller than or equal to the width of the second gate electrode 105 in the second direction Y.
Applicant’s identification of the entire line 105 as the second gate overlying the connection portion 138 is necessarily to achieve the claimed “wherein an orthographic projection of the connection portion on the substrate is located within an orthographic projection of the second gate on the substrate”. Because Applicant’s identification of the region of the second gate of Suzuki is inconsistent with Applicant’s use of the term, consequently Applicant’s arguments are not persuasive and the rejection for maintained over Suzuki and updated in light of the claim amendments as discussed below.
The Examiner notes that Applicant’s annotated drawings are converted to black and white during processing for inclusion into the filewrapper and Applicant’s annotated colored boxes are difficult to view after conversion to black and white.
In order to maintain consistency with the previous office action mailed 04/02/2026, the embodiment of Suzuki’s FIG. 2C is relied upon as the identified region of the connection portion lies within the orthographic projection of the second gate (GL2). However, Suzuki teaches in the embodiment of FIG. 7A a connection portion (31) of reduced width (notches n1) which more closely resembles Applicant’s FIG. 4:
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Suzuki’s entire connection portion (32) in FIG. 7A is entirely encompassed within the second gate (GL2), similar to Applicant’s disclosure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3,5,14-15,17-19 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by US 2023/0135065 A1 to Suzuki et al., “Suzuki”.
Regarding claims 1 and 17, Suzuki discloses (claim 17) a display panel comprising (claim 1) an array substrate (e.g. FIG. 1) having a display region (DR, ¶ [0090]), the array substrate comprising (FIG. 2B,2C or 7A):
a substrate (1, ¶ [0092]); and
a thin film transistor layer (20, ¶ [0092]) on a side of the substrate, wherein the thin film transistor layer comprises a plurality of first thin film transistors (FIG. 1 TFTs 20) arranged in a first direction, and the first thin film transistors are located in a display region (“DR”), wherein each of the first thin film transistors comprises (FIG. 2B) a first gate (“GE1,GL1”, ¶ [0109],[0111],[0113]-[0114]) and a second gate (“GE2,GL2”), and the second gate is located on a side of the first gate (“GE1,GL1”) away from the substrate, the second gates (FIG. 2 second gates GL2) of adjacent ones of the first thin film transistors are connected in the first direction (along IId-IId’), and the first gates of at least two of the first thin film transistors are spaced apart (by FIG. 2C space n1 of width x1,xa or FIG. 7A narrowed region n1) in the first direction (along IId-IId’),
wherein a connection portion (narrowed portion n1 of GL1, see Examiner-annotated figures below) is provided between the first gates (GL1) of at least two of the first thin film transistors in the first direction, and the connection portion connects the first gates (wider w31 portions GL1) of the at least two of the first thin film transistors; and
wherein an orthographic projection of the connection portion on the substrate is located within an orthographic projection of the second gate (GL2) on the substrate.
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Regarding claims 2 and 18, Suzuki discloses the array substrate of claim 1 and the display panel of claim 17, and Suzuki further discloses wherein the first gates (GL1) of adjacent ones of the first thin film transistors are spaced apart in the first direction (spaced apart in regions n1).
Regarding claims 3 and 19, Suzuki discloses the array substrate of claim 2 and the display panel of claim 18, and Suzuki further discloses wherein an orthographic projection of the second gate (GL2) on the substrate overlaps an orthographic projection of the first gate (GL1) on the substrate.
Regarding claim 5, Suzuki discloses the array substrate of claim 2, and Suzuki further teaches wherein the thin film transistor layer further comprises (FIG. 9A, FIG. 10I) a first via hole (CH1, ¶ [0192],[0193]) located between the first gate (GL1) and the second gate (8C/GL2), and the first gate (GL1) and the second gate of each of the first thin film transistors are connected (by connection electrode 6C) in the first via hole in the first direction.
Regarding claim 14, Suzuki discloses the array substrate of claim 1, and Suzuki further discloses wherein the thin film transistor layer comprises at least one first thin film transistor group (i.e. two as pictured) in the first direction (left-right axis), and each of the at least one first thin film transistor group comprises at least two of the first thin film transistors (as pictured); and wherein in the first direction, the first gates (GL1) of adjacent ones of the first thin film transistors in each of the at least one first thin film transistor group are connected (see Examiner-annotated figures with claim 1 above), and the first gates (GL1) of the first thin film transistors in the adjacent ones of the at least one first thin film transistor group are spaced apart (by spacing x1,xa as pictured).
Regarding claim 15, Suzuki discloses the array substrate of claim 14, and Suzuki further discloses wherein each of the at least one first thin film transistor group is provided with a first via hole (FIG. 9A via hole filled with 6C, ¶ [0191]-[0198]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0135065 A1 to Suzuki et al., “Suzuki”, in view of US 2024/0145484 A1 to Ozeki, “Ozeki”.
Regarding claim 4, although Suzuki discloses the array substrate of claim 2, Suzuki fails to clearly teach wherein, in the first direction, an interval between the first gates of adjacent ones of the first thin film transistors is greater than or equal to 1 micron, and the interval between the first gates of adjacent ones of the first thin film transistors is less than or equal to 6.6 microns.
Ozeki teaches (e.g. FIG. 5) wherein an interval between wirings (i.e. interval pitch or pixel pitch) is between 4 μm or more and 8 μm or less (¶ [0078]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Suzuki with a pixel pitch within the claimed range as exemplified by Ozeki in order to achieve high density of pixels which is desired without excessive parasitic capacitance (Ozeki ¶ [0071]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the pixel pitch determines the pixel density making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0135065 A1 to Suzuki et al., “Suzuki”, in view of US 2010/0012940 A1 to Sato, “Sato”.
Regarding claim 16, Suzuki discloses the array substrate of claim 1, and Suzuki further discloses (e.g. FIG. 1) a non-display region (gate drivers GD, source driver DC) located on at least one side of the display region (“DR”).
Although Suzuki teaches similar TFTs in the non-display region (¶ [0125]), Suzuki fails to clearly teach in sufficient detail for anticipation the thin film transistor layer further comprising second
thin film transistors located within the non-display region; wherein the second thin film transistor includes a second source and a second drain, and one of the second source and the second drain of at least one of the second thin film transistors is connected to the second gate electrode of at least one of the first thin film transistors.
Sato teaches (FIG. 1, FIG. 2) a gate driver in a non-display area (“V”, ¶ [0057]) which comprises second thin-film transistors (“GATE DRIVER TFT”s), the second thin film transistor comprising a second source (“ST”) and a second drain (“DT”), and wherein one of the second source and second drain of the at least one second thin film transistors is connected to the second gate (“GT” of “PIXEL TFT”) of at least one of the first thin film transistors (FIG. 2).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Suzuki with a non-display area gate driver TFT as taught by Sato in order to achieve gate driving with high mobility (Sato Abstract).
Allowable Subject Matter
Claims 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Suzuki teaches the array substrate of claim 1 as discussed above.
Prior art e.g. US 2020/0185425 A1 to Hara et al. teaches wherein a first thin film transistor further comprises a first active layer (7a(7), ¶ [0005],[0109],[0145],[0289]) between the first gate (3a(3)) and the second gate (10a(10)), and the first via hole (FIG. 15A(a) opening 11p) is located on a side (toward the right) of the first active layer (7a(7)) in the first direction (x), as discussed previously.
However, prior art fails to reasonably teach or suggest wherein the first thin film transistor further comprises a first active layer between the first gate and the second gate, and the first via hole is located on a side of the first active layer in the first direction as claimed in claim 6 together with all of the limitations of claim 5 and claim 2 and claim 1. Claims 7-11 are objected to as being allowable insofar as they depend upon and include all of the limitations of claims 6,5,2, and 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0253506 A1 to ONODERA et al. teaches (e.g. FIG. 6) a continuous first gate (GL) and a first via hole (CH1) connecting to a second gate (TG).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
Prosecution Insights