The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
2. Claim 1-8 rejected under 35 U.S.C. 103(a) as being unpatentable over Anzai et al. (U.S. Patent 6323551, hereinafter referred to as Anzai) in view of KASHU MASANORI (JP2015-228472A, IDS, machine translated, hereinafter referred to as MASANORI).
As to claim 1, Anzai teaches 1. A semiconductor package, which is provided as a wafer-level chip-size package type semiconductor package (10) having a plurality of terminals (100), wherein the semiconductor package has an elongated and narrow rectangular planar shape, the plurality of terminals are arranged in two columns along a short-side direction (Dl) of the semiconductor package. [see 15, 13, 17 in Fig.1~2]
Anzai may not explicitly teach and each of the terminals comprises a circular body part (111) and a protruding part (112) extending outward from the body part.
MASANORI teaches this limitation [see 32a, 30a, 32b, 30b in Fig. 1 for example]
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Anzai and MASANORI to “use said terminals" in Anzai according to MASANORI, for the further advantage of “suppressing bonding failure of terminal and/ or a short circuit”. […Therefore, it is possible to suppress non-uniformity between the height of the collecting part 32a formed on the land 26a and the height of the collecting part 32b formed on the land 26a. In this way, the height of the assembly 26a can be made appropriate. Therefore, bonding failure of terminal and/ or a short circuit can be suppressed…¶0025]
As to claim 2, Anzai and MASANORI teaches 2. The semiconductor package of claim 1, wherein the protruding part comprises a first straight edge line (112a), and an extension line (L1) of the first straight edge line passes through a gravity center (113) of the body part, and the protruding part is disposed in a counterclockwise direction based on the first straight edge line. [see 30b in Fig. 1 MASANORI]
As to claim 3, Anzai and MASANORI teaches 3. The semiconductor package of claim 1, wherein the protruding part comprises a first straight edge line, and an extension line of the first straight edge line passes through a gravity center of the body part, and the protruding part is disposed in a clockwise direction based on the first straight edge line. [see 30b in Fig. 1 MASANORI]
As to claim 4, Anzai and MASANORI teaches 4. The semiconductor package of claim 2, wherein, in a virtual straight radial line (L11) connected from a gravity center (12) of the semiconductor package to the gravity center of the body part of each of the plurality of terminals, an angle between a first direction (LD11), in which the virtual straight radial line is directed, and a protruding direction of the protruding part of the terminal, through which the straight radial line passes, is greater than about 45o and less than about 165 o. [see 30b in Fig. 1 MASANORI]
As to claim 5, Anzai and MASANORI teaches 5. The semiconductor package of claim 2, wherein the protruding part further comprises a second straight edge line (112b) and a third straight edge line (112c), wherein the third straight edge line is parallel to the first straight edge line, one end point of the third straight edge line is connected to one point of the body part, and the second straight edge line is perpendicularly connected to each of a point of both end points of the first straight edge line (112a), which is not connected to the body part, and the other end point of the third straight edge line (112c). [see 30b in Fig. 1 MASANORI]
As to claim 6, Anzai and MASANORI teaches 6. The semiconductor package of claim 2, wherein the protruding part further comprises a fourth curved edge line (112d), wherein one end point of the fourth curved edge line is connected to a point of both end points of the first straight edge line, which is not connected to the body part, and the other end point of the fourth curved edge line is connected to one point of the body part. [see 30b in Fig. 1 MASANORI]
As to claim 7, Anzai and MASANORI teaches 7. The semiconductor package of claim 1, wherein the protruding part (112) of at least one terminal (110) of the plurality of terminals is configured to invade a virtual division line (11) that divides the plurality of terminals into two columns in the semiconductor package. [see 30b in Fig. 1 MASANORI]
As to claim 8, Anzai and MASANORI teaches 8. The semiconductor package of claim 1, wherein the protruding part (112) of at least one terminal (110) of the plurality of terminals is configured to overlap a virtual division line (11) that divides a short width of the short width and a long width of the semiconductor package into 1/2. [see 30b in Fig. 1 MASANORI]
Conclusion
Claims 1-8 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899