DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, species I, claims 1-24, in the reply filed on May 18, 2026 is acknowledged.
Claims 25-37 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 18, 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed November 8, 2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “isolation layer substantially completely overlaps with the first source/drain layer of the second semiconductor device in a top view” (claim 7); “a thickness of the first source/drain layer and second source/drain layer of the first semiconductor device in the vertical direction is greater than a thickness of the first source/drain layer and second source/drain layer of the second semiconductor device in the vertical direction” (claim 23); and “a height of the channel layer of the first semiconductor device in the vertical direction is different from a height of the channel layer of the second semiconductor device in the vertical direction” (claim 24) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings Figs. 22(b) and 24(d) are objected to because inconsistent shading color for “1027” and “1041”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “an end of … of the first semiconductor device”, as recited in claim 1, is unclear as to an end of which element(s) applicant refers.
The claimed limitation of “second source/drain layer”, as recited in claims 1 (lines 8 and 10), 2, 9, 10, 20 (line 6) and 23, is unclear as to whether said limitation is the same as or different from “second source/drain layer”, as recited in claim 1, lines 5-6.
The claimed limitation of “gate stack”, as recited in claims 1 (lines 8, 10, 16) and 20 (line 6), is unclear as to whether said limitation is the same as or different from “gate stack”, as recited in claim 1, line 6.
The claimed limitation of “a corresponding end of … of the second semiconductor device”, as recited in claim 1, is unclear as to a corresponding end of which element(s) applicant refers.
The claimed limitation of “an end of respective first source/drain layer”, as recited in claim 1, is unclear as to whether said limitation is the same as or different from “an end of the first source/drain layer” and/or “a corresponding end of the first source/drain layer”, as recited in claim 1, lines 8 and/or 10.
The claimed limitation of “respective first source/drain layer”, as recited in claims 1 (line 13) and 2, is unclear as to whether said limitation is the same as or different from “a first source/drain layer”, as recited in claim 1, line 5.
The claimed limitation of “a corresponding end of … of the first semiconductor device and the second semiconductor device”, as recited in claim 1, is unclear as to a corresponding end of which element(s) applicant refers.
The claimed limitation of “respective second source/drain layer”, as recited in claim 1, lines 15-16, is unclear as to whether said limitation is the same as or different from “a second source/drain layer” and/or “second source/drain layer, as recited in claim 1, lines 5-5 and/or 8.
Claims 1, 11 and 12 recite the limitation “the end of the gate stack” in lines 20-21, 2-2 and 6-7, and 2 and 5, respectively. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “an end of the first source/drain layer, second source/drain layer and gate stack of the first semiconductor device”, “a corresponding end of the first source/drain layer, second source/drain layer and gate stack of the second semiconductor device”, “a corresponding end of respective second source/drain layer and gate stack of the first semiconductor device and the second semiconductor device”, as recited in claim 1, lines 9-11 and 15-16.
Claims 1 and 12 recites the limitation “the end of the second source/drain layer” in lines 22-23, lines 3 and 6, respectively. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “an end of the first source/drain layer, second source/drain layer and gate stack of the first semiconductor device”, “a corresponding end of the first source/drain layer, second source/drain layer and gate stack of the second semiconductor device”, “a corresponding end of respective second source/drain layer and gate stack of the first semiconductor device and the second semiconductor device”, as recited in claim 1, lines 9-11 and 15-16.
Claims 2 and 9 recite the limitation “the another end of …” in lines 2 and 1-4, respectively. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to the another end of which element applicant refers; and whether said limitation is the same as or different from “another end of the second source/drain layer”, as recited in claim 1.
The claimed limitation of “respective gate stack”, as recited in claim 2, is unclear as to whether said limitation is the same as or different from “gate stack”, as recited in claim 1, lines 6, 8, 10 and/or 16.
The claimed limitation of “a straight line”, as recited in claim 4, line 4, is unclear as to whether said limitation is the same as or different from “a straight line”, as recited in claim 4, line 3.
The claimed limitation of “a zigzag shape”, as recited in claim 4, line 7, is unclear as to whether said limitation is the same as or different from “a zigzag shape”, as recited in claim 4, line 6.
The term “substantially” in claims 7, 9-11, 13 and 14, is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The claimed limitation of “another end of …”, as recited in claim 10, is unclear as to another end of which element(s) applicant refers; and as to whether said limitation is the same as or different from “another end of the second source/drain layer”, as recited in claim 1.
The claimed limitation of “the end of … of the first semiconductor device”, as recited in claim 10, is unclear as to the end of which element(s) applicant refers.
Claim 10 recites the limitation “the end of … of the second semiconductor device” in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to the end of which element applicant; and whether said limitation is the same as or different from “a corresponding end of the first source/drain layer, second source/drain and …” and/or “a corresponding end of respective second source/drain layer”, as recited in claim 1.
The claimed limitation of “another end of the gate stack”, as recited in claim 11, is unclear as to whether said limitation is the same as or different from “another end of the gate stack”, as recited in claim 1.
The claimed limitation of “a correspond end of the second source drain layer”, as recited in claim 11, lines 4-5, is unclear as to whether said limitation is the same as or different from “an end of the first source/drain layer, … of the first semiconductor device”, “a corresponding end of respective source/drain layer … of the first semiconductor device” and/or “the end of the second source/drain layer”, as recited in claim 1.
The claimed limitation of “a correspond end of the second source drain layer”, as recited in claim 11, lines 8-9, is unclear as to whether said limitation is the same as or different from “a corresponding end of the first source/drain layer, … of the second semiconductor device”, and/or “the end of the second source/drain layer”, as recited in claim 1.
The term “about” in claim 17, is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The claimed limitation of “the gate stack has a substantially same … width on two opposite sides of the channel layer”, as recited in claim 1, is unclear as to compare with which element that the gate stack has a substantially same … width applicant refers.
Claim 13 recites the limitation “the first width” in line 3. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a substantially same first width”, as recited in claim 13, line 2.
Claim 13 recites the limitation “the second width” in line 6. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a substantially same second width”, as recited in claim 13, line 5.
The claimed limitation of “the channel layer”, as recited in claims 15 and 18, is unclear as to the channel layer of which element applicant refers.
The claimed limitation of “an end of … of the second semiconductor device”, as recited in claim 20, is unclear as to whether said limitation is the same as or different from “a correspond end of the first source/drain layer, … of the second semiconductor device”, “a corresponding end of respective second source/drain … and the second semiconductor device”, as recited in claim 1.
The claimed limitation of “an end of … of the third semiconductor device”, as recited in claim 20, is unclear as to an end of which element(s) applicant refers.
The claimed limitation of “second source/drain layer”, as recited in claim 20, line 8, is unclear as to whether said limitation is the same as or different from “second source/drain layer”, as recited in claim 20, line 4.
The claimed limitation of “gate stack”, as recited in claims 20 (line 8) and 21, is unclear as to whether said limitation is the same as or different from “gate stack”, as recited in claim 20, line 5.
The claimed limitations of “an end of the first source/drain layer” and “a corresponding end of the second source/drain layer and gate stack”, as recited in claim 21, is unclear as to whether said limitation is the same as or different from “an end of the first source/drain layer, second source/drain layer and gate stack of the third semiconductor device”, as recited in claim 20.
The claimed limitation of “a corresponding end of … the third semiconductor device”, as recited in claim 21, is unclear as to a corresponding end of which element applicant refers.
Claim 21 recites the limitation “the end of the gate stack” in line 8. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “an end of the first source/drain layer, second source/drain layer and gate stack”, as recited in claim 20 and/or “a corresponding end of the second source/drain layer and gate stack”, as recited in claim 21, line 4-5.
Claim 21 recites the limitation “the end of the second source/drain layer” in line 10. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “an end of the first source/drain layer, second source/drain layer and gate stack”, as recited in claim 20 and/or “a corresponding end of the second source/drain layer and gate stack”, as recited in claim 21, line 4-5.
Claim 22 recites the limitation “the top” in line 2. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as the top of which element applicant refers.
The claimed limitations of “a thickness … of … semiconductor device”, as recited in claim 23, is unclear as to a thickness of which element(s) applicant refers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 9-17 and 20-24, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (2021/0351297) in view of Lu et al.(2017/0358594).
As for claim 1, Zhu show in Fig. 32 and related text a semiconductor apparatus, comprising:
a first semiconductor device 1003/1005a/1007-1a/1045/1047 and a second semiconductor device 1007-2a/1009a/1011-1a which are stacked on the substrate in a vertical direction, wherein each of the first semiconductor device and the second semiconductor device comprises a first source/drain layer 1003/1007-2a, a channel layer 1005a/1009a and a second source/drain layer 1007-1a/1011-1a which are stacked in sequence in the vertical direction, and a gate stack 1045/1047 surrounding a periphery of the channel layer,
wherein an end of the first source/drain layer, second source/drain layer and gate stack of the first semiconductor device in a first direction protrudes in the first direction relative to a corresponding end of the first source/drain layer, second source/drain layer and gate stack of the second semiconductor device in the first direction, so as to form a first step, and a second step is defined by the second semiconductor device.
Zhu does not disclose an end of respective first source/drain layer of the first semiconductor device and the second semiconductor device in a second direction intersecting with the first direction protrudes in the second direction relative to a corresponding end of respective second source/drain layer and gate stack of the first semiconductor device and the second semiconductor device in the second direction, so as to respectively form a first sub-step and a second sub-step, wherein the first sub-step is on the first step, and the second sub-step is on the second step, wherein in each of the first semiconductor device and the second semiconductor device, another end of the gate stack in the second direction, which is opposite to the end of the gate stack in the second direction, protrudes in the second direction relative to another end of the second source/drain layer in the second direction, which is opposite to the end of the second source/drain layer in the second direction.
Lu et al. teach in Fig. 4 and related text a first sub-step and a second sub-step are formed in the first semiconductor device and the second semiconductor device in a second direction intersecting with the first direction, wherein the first sub-step is on the first step, and the second sub-step is on the second step.
Zhu and Lu et al. are analogous art because they are directed to a memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhu with the specified feature(s) of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form a first sub-step on the first step and a second-sub-step on the second step in a second direction, as taught by Lu et al., in Zhu's device, in order to reduce size and cost of the device.
Therefore, the combined device shows an end of respective first source/drain layer of the first semiconductor device and the second semiconductor device in a second direction intersecting with the first direction protrudes in the second direction relative to a corresponding end of respective second source/drain layer and gate stack of the first semiconductor device and the second semiconductor device in the second direction, so as to respectively form a first sub-step and a second sub-step, wherein the first sub-step is on the first step, and the second sub-step is on the second step,
wherein in each of the first semiconductor device and the second semiconductor device, another end of the gate stack in the second direction, which is opposite to the end of the gate stack in the second direction, protrudes in the second direction relative to another end of the second source/drain layer in the second direction, which is opposite to the end of the second source/drain layer in the second direction.
As for claim 2, the combined device shows a dielectric 1043 connected to the another end of respective first source/drain layer and second source/drain layer of the first semiconductor device and the second semiconductor device in the second direction, wherein the dielectric respectively sandwiches respective gate stack of the first semiconductor device and the second semiconductor device in the vertical direction (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claim 9, the combined device shows the another end of the first source/drain layer and second source/drain layer of the first semiconductor device in the second direction is substantially aligned in the vertical direction with the another end of the first source/drain layer and second source/drain layer of the second semiconductor device in the second direction (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claim 10, the combined device shows another end of the first source/drain layer and second source/drain layer of the first semiconductor device in the first direction, which is opposite to the end of the first source/drain layer and second source/drain layer of the first semiconductor device in the first direction, is substantially aligned in the vertical direction with another end of the first source/drain layer and second source/drain layer of the second semiconductor device in the first direction, which is opposite to the end of the first source/drain layer and second source/drain layer of the second semiconductor device in the first direction (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claim 11, the combined device shows in the first semiconductor device, the end of the gate stack in the first direction and another end of the gate stack in the first direction opposite to the end of the gate stack are substantially aligned in the vertical direction with a corresponding end of the second source/drain layer,
in the second semiconductor device, the end of the gate stack in the first direction and another end of the gate stack in the first direction opposite to the end of the gate stack are substantially aligned in the vertical direction with a corresponding end of the second source/drain layer direction (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claim 12, the combined device shows the end of the gate stack of the first semiconductor device in the second direction is recessed in the second direction relative to the end of the second source/drain layer of the first semiconductor device in the second direction,
the end of the gate stack of the second semiconductor device in the second direction is recessed in the second direction relative to the end of the second source/drain layer of the second semiconductor device in the second direction (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claim 13, the combined device shows in the first semiconductor device, the gate stack has a substantially same first width (arbitrarily chosen) on two opposite sides of the channel layer in the first direction, and the first width is measured in the first direction,
in the second semiconductor device, the gate stack has a substantially same second width (arbitrarily chosen) on two opposite sides of the channel layer in the first direction, and the second width is measured in the first direction (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claim 14, the combined device shows the first width is substantially equal to the second width.
As for claim 15, the combined device shows the channel layer has a first dimension (arbitrarily chosen) in the first direction, a second dimension (arbitrarily chosen) in the second direction and a third dimension (arbitrarily chosen) in the vertical direction, wherein the second dimension is less than the first dimension and the third dimension, so that the channel layer is in a form of a nanosheet extending along the first direction, and a thickness of the nanosheet is formed by the second dimension (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claims 16 and 17, Zhu and Lu et al. disclosed substantially the entire claimed invention, as applied to claim 15 above, except the first dimension of the channel layer of the first semiconductor device is greater than the first dimension of the channel layer of the second semiconductor device (claim 16) and the first dimension of the channel layer of the first semiconductor device is greater than the first dimension of the channel layer of the second semiconductor device by about: a size of the first step in the first direction (claim 17).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the first dimension of the channel layer of the first semiconductor device being greater than the first dimension of the channel layer of the second semiconductor device, and the first dimension of the channel layer of the first semiconductor device being greater than the first dimension of the channel layer of the second semiconductor device by about: a size of the first step in the first direction, in order to use an application which requires different power memory devices, and improve the performance of the device. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
As for claim 20, the combined device shows a third semiconductor device 1011-2a/1013a/1015a/1045/1047 stacked on the second semiconductor device in the vertical direction, wherein the third semiconductor device comprises a first source/drain layer 1011-2a, a channel layer 1013a and a second source/drain layer 1015a which are stacked in sequence in the vertical direction, and a gate stack 1045/1047 surrounding a periphery of the channel layer of the third semiconductor device,
wherein an end of the first source/drain layer, second source/drain layer and gate stack of the second semiconductor device in the first direction protrudes in the first direction relative to an end of the first source/drain layer, second source/drain layer and gate stack of the third semiconductor device in the first direction, so as to form the second step, wherein the second sub-step is on the second step (Zhu: Fig. 32).
As for claim 21, the combined device shows a third step is defined by the third semiconductor device,
wherein an end of the first source/drain layer of the third semiconductor device in the second direction protrudes in the second direction relative to a corresponding end of the second source/drain layer and gate stack of the third semiconductor device in the second direction, so as form a third sub-step, wherein the third sub-step is on the third step,
wherein in the third semiconductor device, another end of the gate stack in the second direction, which is opposite to the end of the gate stack in the second direction, protrudes in the second direction relative to another end of the second source/drain layer in the second direction, which is opposite to the end of the second source/drain layer in the second direction (Zhu: Fig. 32 in combined with Lu: Fig. 4).
As for claim 22, the combined device shows the second semiconductor device is a device on the top, and the second step is formed by the first source/drain layer, second source/drain layer and gate stack of the second semiconductor device (Zhu: Fig. 32).
As for claim 23, the combined device shows a thickness (arbitrarily chosen) of the first source/drain layer and second source/drain layer of the first semiconductor device in the vertical direction is greater than a thickness (arbitrarily chosen) of the first source/drain layer and second source/drain layer of the second semiconductor device in the vertical direction (Zhu: Fig. 32).
As for claim 24, the combined device shows a height (arbitrarily chosen) of the channel layer of the first semiconductor device in the vertical direction is different from a height (arbitrarily chosen) of the channel layer of the second semiconductor device in the vertical direction (Zhu: Fig. 32).
Allowable Subject Matter
Claims 3-8, 18 and 19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “a first contact portion, a second contact portion and a third contact portion that are arranged in the second direction; a fourth contact portion, a fifth contact portion and a sixth contact portion that are arranged in the second direction, wherein the first contact portion, the second contact portion and the third contact portion are located above the first step, and the fourth contact portion, the fifth contact portion and the sixth contact portion are located above the second step, wherein the first contact portion is located above the first sub-step and lands on the first source/drain layer of the first semiconductor device, the second contact portion lands on the second source/drain layer of the first semiconductor device, and the third contact portion is close to the another end of the gate stack of the first semiconductor device in the second direction and lands on the gate stack of the first semiconductor device, wherein the fourth contact portion is located above the second sub-step and lands on the first source/drain layer of the second semiconductor device, the fifth contact portion lands on the second source/drain layer of the second semiconductor device, and the sixth contact portion is close to the another end of the gate stack of the second semiconductor device in the second direction and lands on the gate stack of the second semiconductor device”, as recited in claim 3; “an isolation layer located between the first semiconductor device and the second semiconductor device in the vertical direction”, as recited in claim 5; and “the channel layer of each of the first semiconductor device and the second semiconductor device is in a shape of C in a cross-section perpendicular to the first direction”, as recited in claim 18.
Claims 3-8, 18 and 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/MEIYA LI/Primary Examiner, Art Unit 2811
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