Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/10/2023, 6/17/2025, 10/20/2025 and 2/27/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 23 objected to because of the following informalities: the claim appears to have a typographical error "the apparatus claim 21 further comprising ". For the purpose of examination, the examiner will interpret the above limitation as " the apparatus of claim 21 further comprising ". Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al. US 2014/0322932.
Re claim 21, Tran teaches an apparatus (fig1), comprising:
a semiconductor chip package (102, fig1A, [19]), the semiconductor chip package comprising a substrate (108, fig1A, [19]), the substrate comprising side I/Os (112 with 114a-b, fig1B, [20]), the side I/Os coupled to I/Os of a semiconductor chip (110, 120, fig1A, [24]) within the semiconductor chip package.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22-24, 26-27, 30 and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. US 2014/0322932 in view of Klein et al. US 2020/0411410.
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Re claim 22, Tran does not explicitly show the apparatus of claim 21 wherein the side I/Os and an integrated heat spreader are on a same side of the substrate.
Klein teaches a semiconductor chip package (104, fig1 and 2A, [31]) and an integrated heat spreader (105, 202 and 219, fig1 and 2A, [37, 38]) are on a same side of the substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran and Klein to form heat sink in fig1 around the chip package 102 of Tran. The motivation to do so is to achieve high TDP and reduce damage by preventing overheating (Klein, [1]).
Re claim 23, Tran does not explicitly show the apparatus of claim 21 further comprising a cooling assembly that is mechanically integrated with the semiconductor chip package, the cooling assembly comprising a passageway located between a base of a cooling mass and a bolster plate, the passageway to guide a cable connector to the side I/Os.
Klein teaches a semiconductor chip package (104, fig1, [31]) and an integrated heat spreader(105, 202 and 219, fig1 and 2A, [37, 38]) are on a same side of the substrate, a cooling assembly (103-105, fig1, [31]) that is mechanically integrated with the semiconductor chip package (104, fig1, [31]), the cooling assembly comprising a passageway (space between 202 and 101, fig2A, [38]) located between a base (202, fig2A, [38]) of a cooling mass (219, 202, 105, fig2A) and a bolster plate (101, fig2A, [40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran and Klein to form heat sink in fig1 around the chip package 102 of Tran with the space between 202 and 101 guide the cable connector of Tran 132 in fig1A to the side I/Os of Tran 112 in fig1A. The motivation to do so is to achieve high TDP and reduce damage by preventing overheating (Klein, [1]).
Re claim 24,Tran modified above teaches the apparatus of claim 23 wherein a spring (Tran, spring contact 350a/b, fig3, [36]) that is mechanically coupled to the cable connector (Tran, 340a/b, fig3, [37]]) is to be compressed when the cable connector is mated with the side I/Os.
Re claim 26,Tran teaches an apparatus (fig1), comprising:
a semiconductor chip package (102, fig1A, [19]), the semiconductor chip package comprising side I/Os (112 with 114a-b, fig1B, [20]), the side I/Os coupled to I/Os of a semiconductor chip (110, 120, fig1A, [24]) within the semiconductor chip package.
Tran does not explicitly show a cooling assembly.
Klein teaches a cooling assembly (103-105, fig1, [31]) that is mechanically integrated with the semiconductor chip package (104, fig1, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran and Klein to form heat sink in fig1 around the chip package 102 of Tran. The motivation to do so is to achieve high TDP and reduce damage by preventing overheating (Klein, [1]).
Tran in view of Klein teaches at least a portion of a cooling assembly (Klein, 103-105, fig2A, [31]) that is to be mechanically integrated with a semiconductor chip package (Tran, 102, fig1A, [19]), the at least a portion of the cooling assembly comprising a passageway (space between 202 and 101 in fig2A of Klein) that is to be located between a base (Klein, 202, fig2A, [38]) of a cooling mass of the cooling assembly and a bolster plate (Klein, 101, fig2A, [40]) of the cooling assembly, the passageway to guide a cable connector (Tran, 128, fig1 and 3, [32]) to side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3), the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) to couple to first I/Os (Tran, I/O between 110/120 and 108, fig1A) of a semiconductor chip (Tran, 108, 110 and 120, fig1A, [24]) within the semiconductor chip package (Tran, 102, fig1A, [19]), the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) to be located between the base (Klein, 202, fig2A, [38]) of the cooling mass and an electronic circuit board (Tran, 106, fig1A, [19]; Klein, 106, fig2A, [31]) that is to be between the bolster plate (Klein, 101, fig2A, [40]) and a back plate (Klein, 103, fig2A, [31]) and is to couple to second I/Os (I/O between socket layer 109 and 108 of Tran in fig1A) of the semiconductor chip through a socket (Tran, 109, fig1A, [19]; Klein, 102, fig2, [31]) that the semiconductor chip package (Tran, 108, fig1A, [19]) is to be plugged into.
Re claim 27, Tran modified above teaches the apparatus of claim 26 further comprising a spring (Tran, spring contact 350a/b, fig3, [36]) that is to be mechanically coupled to the cable connector (Tran, 128, fig1 and 3, [32]) and that is to be compressed when the cable connector (Tran, 128, fig1 and 3, [32]) is connected to the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3).
Re claim 30, Tran modified above teaches the apparatus of claim 26 wherein the passageway (space between 202 and 101 in fig2A of Klein) is formed in a chip package carrier of the cooling assembly (cable connector 128 of Tran attached to side of device Klein 104 in fig1).
Re claim 33, Tran modified above teaches the apparatus of claim 26 wherein the semiconductor chip package is to have an integrated heat spreader (Klein, 219, fig2A, [38]) mounted to a substrate (Tran, 108, fig1A, [19]), the substrate having additional surface area (Tran 112 extends beyond socket 109. Heat spreader 219 of Klein in fig2A formed inside footprint of socket 102 in fig2A) that extends beyond a footprint of the integrated heat spreader (Klein, 219, fig2A, [38]), the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) residing on the additional surface area of the substrate.
Re claim 34, Tran modified above teaches the apparatus of claim 26 wherein the socket (Tran, 109, fig1A, [19]) is mounted to an interposer (Tran, 108, fig1A, [19]) that is mounted to the electronic circuit board (Tran, 106, fig1A, [19]) and the side I/Os are on the interposer (Tran, 112 on 108 with 114a-b in fig1A/B).
Claim(s) 25, 28-29, 31 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. US 2014/0322932 in view of Klein et al. US 2020/0411410 and Tsai US 2012/0015561.
Re claim 25, Tran does not explicitly show the apparatus of claim 24 further comprising a latch, the spring to be between the latch and the cable connector when the cable connector is mated to the side I/Os.
Tsai teaches detail of interconnect connector (fig34), comprising a latch (38, fig34, [116]), the spring contacts (40, fig34, [117]) to be between the latch (38, fig34, [116]) and the cable connector (20, fig34, [114]) when the cable connector (20, fig34, [114]) is mated to the side I/Os (90, fig37, [120]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran modified above and Tsai to form a casing as 30 in fig34 of Tsai around the connector 128 of Tran. The motivation to do so is to provide a secure contact with reliable contact (Tsai, [132]).
Re claim 28, Tran does not explicitly show the apparatus of claim 27 the at least a portion of the cooling assembly further comprises a latch, the spring to be between the latch and the cable connector when the cable connector is connected to the side I/Os.
Tsai teaches detail of interconnect connector (fig34), comprising a latch (38, fig34, [116]), the spring (40, fig34, [117]) to be between the latch (38, fig34, [116]) and the cable connector (20, fig34, [114]) when the cable connector is connected to the side I/Os (90, fig37, [120]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran modified above and Tsai to form a casing as 30 in fig34 of Tsai around the connector 128 of Tran. The motivation to do so is to provide a secure contact with reliable contact (Tsai, [132]).
Re claim 29, Tran modified above teaches the apparatus of claim 28 wherein a chip package carrier of the cooling assembly further comprises a groove (Tsai, space on side of 90, fig35) to guide movement of the latch (Tsai, 38, fig34, [116]).
Re claim 31, Tran does not explicitly show the apparatus of claim 26 wherein the at least a portion of the cooling assembly further comprises a latch, the latch to vertically move the cable connector into electro-mechanical contact with the side I/Os.
Tsai teaches detail of interconnect connector (fig34), comprising a latch (38, fig34, [116]), the latch to vertically move the cable connector into electro-mechanical contact with the side I/Os (fig35-37).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran modified above and Tsai to form a casing as 30 in fig34 of Tsai around the connector 128 of Tran. The motivation to do so is to provide a secure contact with reliable contact (Tsai, [132]).
Re claim 35, Tran modified above teaches the apparatus of claim 26 further comprising a groove (Tsai, space on side of 90, fig35) next to the side I/Os (Tsai, 90, fig35) into which a spring (Trai, 40, fig35) that is attached to the cable connector is to slide into.
Claim(s) 36-37 are rejected under 35 U.S.C. 103 as being unpatentable over Ganguli et al. US 2021/0058299 in view of Tran et al. US 2014/0322932 and Klein et al. US 2020/0411410.
Re claim 36, Ganguli teaches a data center (fig16), comprising:
a plurality of racks (1606, fig16, [84]), the plurality of racks comprising electronic systems communicatively coupled through one or more networks (fig16, [84]).
Ganguli does not explicitly show detail of the electronic systems with a cooling assembly.
Tran teaches at least one of the electronic systems comprising a semiconductor chip package (102, fig1A, [19]).
Klein teaches a cooling assembly (103-105, fig1, [31]) that is mechanically integrated with the semiconductor chip package (104, fig1, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ganguli, Tran and Klein to form heat sink in fig1 around the chip package 102 of Tran used in the rack of Ganguli. The motivation to do so is to achieve low electrical signal loss (Tran, [27]), high TDP and reduced damage by preventing overheating (Klein, [1]).
Ganguli in view of Tran and Klein teaches at least one of the electronic systems comprising a semiconductor chip package (Klein, 104, fig1, [31]; Tran, 102, fig1A, [19]) and a cooling assembly (Klein, 103-105, fig2A, [31]) that is mechanically integrated with the semiconductor chip package,
the cooling assembly comprising a cooling mass (Klein, 105, fig2A, [31]), a bolster plate (Klein, 101, fig2A, [40]) and a back plate (Klein, 103, fig2A, [31]), an electronic circuit board (Klein, PCB 106, fig2A, [31]) located between the bolster plate (Klein, 101, fig2A, [40]) and the back plate (Klein, 103, fig2A, [31]),
the cooling assembly comprising a passageway (space between 202 and 101 in fig2A of Klein) located between a base (Klein, 202, fig2A, [38]) of the cooling mass and the bolster plate (Klein, 101, fig2A, [40]), a cable (Tran, 104, fig1A, [27]) within the passageway,
a connector (Tran, 128, fig1 and 3, [32]) of the cable mated to side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3), the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) coupled to first I/Os of a semiconductor chip (Tran, I/O between 110/120 and 108, fig1A, [24]) within the semiconductor chip package, the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) located between the base (Klein, 202, fig2A, [38]) of the cooling mass and the electronic circuit board (Klein, PCB 106, fig2A, [31]; Tran, PCB 106, fig1A, [19]), the electronic circuit board coupled to second I/Os (I/O between socket layer 109 and 108 of Tran in fig1A) of the semiconductor chip through a socket (Klein, 102, fig2, [31]; Tran, 109, fig1A, [19]) that the semiconductor chip package is plugged into.
Re claim 37, Ganguli modified above teaches the apparatus of claim 36 further comprising a spring (Tran, spring contact 350a/b, fig3, [36]) that is mechanically coupled to the cable connector (Tran, 128, fig1 and 3, [32]), the spring being compressed, the cable connector connected to the side I/Os (Tran, fig1 and 3).
Claim(s) 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Ganguli et al. US 2021/0058299 in view of Tran et al. US 2014/0322932, Klein et al. US 2020/0411410 and Tsai US 2012/0015561.
Re claim 38, Ganguli does not explicitly show the apparatus of claim 37 wherein the cooling assembly further comprises a latch, the spring located between the latch and the cable connector.
Tsai teaches detail of interconnect connector (fig34), comprising a latch (38, fig34, [116]), the spring contacts (40, fig34, [117]) to be between the latch (38, fig34, [116]) and the cable connector (20, fig34, [114]) when the cable connector (20, fig34, [114]) is mated to the side I/Os (90, fig37, [120]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ganguli modified above and Tsai to form a casing as 30 in fig34 of Tsai around the connector 128 of Tran. The motivation to do so is to provide a secure contact with reliable contact (Tsai, [132]).
Re claim 39, Ganguli modified above teaches the apparatus of claim 38 wherein a chip package carrier of the cooling assembly further comprises a groove (Tsai, space on side of 90, fig35) to guide movement of the latch (Tsai, 38, fig34, [116]).
Re claim 40, Ganguli modified above teaches the apparatus of claim 36 wherein the passageway (space between 202 and 101 in fig2A of Klein) is formed in a chip package carrier of the cooling assembly (Klein, fig2A).
Allowable Subject Matter
Claim 32 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to provide a reliable electrical connector with lower signal loss.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812