Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/4/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 28 objected because of the following informalities: the claim appears to have a typographical error "The apparatus of claim 27 " with claim 27 being canceled. For the purpose of examination, the examiner will interpret the above limitation as " The apparatus claim 26". Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al. US 2014/0322932.
Re claim 21, Tran teaches an apparatus (fig1), comprising:
a semiconductor chip package (110, 120 and 108, fig1A, [19, 24]) wherein the semiconductor chip package has a footprint (footprint of 108, fig1A),
the semiconductor chip package (110, 120 and 108, fig1A, [19, 24]) comprising a substrate (108, fig1A, [19]), the substrate comprising side input/outputs I/Os (112 with 114a-b at end 128, fig1A and 1B, [20, 27]), the side I/Os coupled to I/Os of a semiconductor chip (110, 120, fig1A, [24]) within the semiconductor chip package; and
a carrier (123 or 106, fig1A, [29]) around a portion of the semiconductor chip package (110, 120 and 108, fig1A, [19, 24]) wherein the carrier comprises a region that extends beyond the footprint (footprint of 108, fig1A) and the region is over the side I/Os (I/O at end 128, fig1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. US 2014/0322932 in view of Klein et al. US 2020/0411410.
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Re claim 22, Tran does not explicitly show the apparatus of claim 21 wherein the side I/Os and an integrated heat spreader are on a same side of the substrate.
Klein teaches a semiconductor chip package (104, fig1 and 2A, [31]) and an integrated heat spreader (105, 202 and 219, fig1 and 2A, [37, 38]) on a same side of the substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran and Klein to form heat sink in fig1 around the chip package 102 of Tran. The motivation to do so is to achieve high TDP and reduce damage by preventing overheating (Klein, [1]).
Re claim 23, Tran does not explicitly show the apparatus of claim 21 further comprising a cooling assembly that is mechanically integrated with the semiconductor chip package, the cooling assembly comprising a passageway located between a base of a cooling mass and a bolster plate, the passageway to guide a cable connector to the side I/Os.
Klein teaches a semiconductor chip package (104, fig1, [31]) and an integrated heat spreader(105, 202 and 219, fig1 and 2A, [37, 38]) are on a same side of the substrate, a cooling assembly (103-105, fig1, [31]) that is mechanically integrated with the semiconductor chip package (104, fig1, [31]), the cooling assembly comprising a passageway (space between 202 and 101, fig2A, [38]) located between a base (202, fig2A, [38]) of a cooling mass (219, 202, 105, fig2A) and a bolster plate (101, fig2A, [40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran and Klein to form heat sink in fig1 around the chip package 102 of Tran with the space between 202 and 101 guide the cable connector of Tran 132 in fig1A to the side I/Os of Tran 112 in fig1A. The motivation to do so is to achieve high TDP and reduce damage by preventing overheating (Klein, [1]).
Claim(s) 24 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. US 2014/0322932 in view of Tsai US 2012/0015561.
Re claim 24, Tran does not explicitly show the apparatus of claim 21 also comprising a cable connector wherein the cable connector is operationally coupled to the side I/Os, wherein the cable connector comprises a first spring on a first surface of the cable connector and a second spring on a second surface of the cable connector, and wherein I/Os of the cable connector are between the first spring and the second spring.
Tsai teaches detail of interconnect connector (fig34), comprising a cable connector (fig33) comprises a first spring (upper spring in 31, fig34, [77]) on a first surface of the cable connector (top surface of 30, fig34, [77]) and a second spring on a second surface of the cable connector (bottom spring located on bottom surface of 30, fig34, [77]), and wherein I/Os of the cable connector (50, fig34, [113]) are between the first spring and the second spring.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran and Tsai to form a casing as 30 in fig34 of Tsai around the connector 128 of Tran. The motivation to do so is to provide a secure contact with reliable contact (Tsai, [132]).
Re claim 41, Tran does not explicitly show the apparatus of claim 21 wherein the substrate comprises a groove into which a spring on a surface of a cable connector is capable of fitting.
Tsai teaches wherein the substrate comprises a groove (space on top and bottom side of 90, fig35) into which a spring on a surface of a cable connector is capable of fitting (spring on top or bottom surface of 30, fig35).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tran and Tsai to form a casing as 30 in fig34 of Tsai around the connector 128 of Tran adjusted with grooves as in Tsai fig35. The motivation to do so is to provide a secure contact with reliable contact (Tsai, [132]).
Claim(s) 36 is rejected under 35 U.S.C. 103 as being unpatentable over Ganguli et al. US 2021/0058299 in view of Tran et al. US 2014/0322932 and Klein et al. US 2020/0411410.
Re claim 36, Ganguli teaches a data center (fig16), comprising:
a plurality of racks (1606, fig16, [84]), the plurality of racks comprising electronic systems communicatively coupled through one or more networks (fig16, [84]).
Ganguli does not explicitly show detail of the electronic systems with a cooling assembly.
Tran teaches at least one of the electronic systems comprising a semiconductor chip package (102, fig1A, [19]).
Klein teaches a cooling assembly (103-105, fig1, [31]) that is mechanically integrated with the semiconductor chip package (104, fig1, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ganguli, Tran and Klein to form heat sink in fig1 around the chip package 102 of Tran used in the rack of Ganguli. The motivation to do so is to achieve low electrical signal loss (Tran, [27]), high TDP and reduced damage by preventing overheating (Klein, [1]).
Ganguli in view of Tran and Klein teaches at least one of the electronic systems comprising a semiconductor chip package (Klein, 104, fig1, [31]; Tran, 102, fig1A, [19]), an electronic circuit board (Klein, PCB 106, fig2A, [31]; Tran, 106, fig1A, [19]) and a cooling assembly (Klein, 103-105, fig2A, [31]) that is mechanically integrated with the semiconductor chip package,
the cooling assembly comprising a cooling mass (Klein, 105, fig2A, [31]), a bolster plate (Klein, 101, fig2A, [40]) and a back plate (Klein, 103, fig2A, [31]), wherein the electronic circuit board (Klein, PCB 106, fig2A, [31]) is located between the bolster plate (Klein, 101, fig2A, [40]) and the back plate (Klein, 103, fig2A, [31]),
the cooling assembly also comprising a passageway (space between 202 and 101 in fig2A of Klein) located between a base (Klein, 202, fig2A, [38]) of the cooling mass and the bolster plate (Klein, 101, fig2A, [40]), a cable (Tran, 104, fig1A, [27]) within the passageway,
a connector (Tran, 128, fig1 and 3, [32]) of the cable mated to side input/outputs I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3), the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) coupled to first I/Os of a semiconductor chip (Tran, I/O between 110/120 and 108, fig1A, [24]) within the semiconductor chip package, the side I/Os (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) located between the base (Klein, 202, fig2A, [38]) of the cooling mass and the electronic circuit board (Klein, PCB 106, fig2A, [31]; Tran, PCB 106, fig1A, [19]), the electronic circuit board coupled to second I/Os (I/O between socket layer 109 and 108 of Tran in fig1A) of the semiconductor chip through a socket (Klein, 102, fig2, [31]; Tran, 109, fig1A, [19]) that the semiconductor chip package is plugged into.
Wherein a carrier (Tran, 123, fig1A, [29]) encircles a portion of the semiconductor chip package (Klein, 104, fig1, [31]; Tran, 102, fig1A, [19]) and wherein the side IOs (Tran, 112 with 114a-b in fig1A/B or 336 with 338a-b in fig3) are between a portion of the carrier (Tran, top part of 123, fig1A, [29]) and the bolster plate (Klein, 101, fig2A, [40]).
Response to Arguments
Regarding arguments about all the claims applicant's arguments have been fully considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Allowable Subject Matter
Claims 26, 28-30 and 33-35 are allowed.
Claim 25 and 37-40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to provide a reliable electrical connector with lower signal loss.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOMING LIU/Examiner, Art Unit 2812
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