DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/17/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The amendment filed on 4/17/2026 has been considered.
Response to Arguments
Applicant's arguments with respect to claims 11, 13-24 and 26-30 have been considered but are moot because the arguments do not apply to all of the references being used in the current rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11, 13, 16-24 and 26-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaneko (US 2015/0014020) in view of Kaneko (US 2015/0014027).
Regarding claim 11, Kaneko020 discloses, in at least figures 1A-2 and related text, a circuit board comprising:
an insulating layer (12, [26]); and
a circuit layer (11/21/22, [26]) disposed on the insulating layer (12, [26]), wherein the circuit layer (11/21/22, [26]) includes a first pad (21, [26]) having a first width (width of 21, figures) along a horizontal direction (horizontal direction, figures), and a second pad (11, [26]) having a second width (width of 11, figures) along the horizontal direction (horizontal direction, figures), and a trace (22, [26]) having a third width (width of 22, figure 2) along the horizontal direction (horizontal direction, figures),
wherein the second width (width of 11, figures) is greater than the first width (width of 21, figures),
wherein the first width (width of 21, figures) is greater than the third width (width of 22, figure 2),
wherein the first pad (21, [26]) includes a recess (area of depth D2, figures) provided on an upper surface (upper surface of 21, figures) thereof.
Kaneko020 does not explicitly disclose a third stepped portion is provided between an upper surface of the trace and an upper surface of the insulating layer.
Kaneko027 teaches, in at least figures 1A-1C and related text, the device comprising a third stepped portion is provided between an upper surface of the trace (21, [21]) and an upper surface of the insulating layer (12, [21]), for the purpose of providing a wiring board, etc. having pads which can enhance the reliability of connections with connection targets ([8]).
Kaneko020 and Kaneko027 are analogous art because they both are directed to circuit board and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kaneko020 with the specified features of Kaneko027 because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Kaneko020 to have the third stepped portion being provided between an upper surface of the trace and an upper surface of the insulating layer, as taught by Kaneko027, for the purpose of providing a wiring board, etc. having pads which can enhance the reliability of connections with connection targets ([8], Kaneko027).
Regarding claim 13, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 11 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, the first pad (21, [26]) includes a 1-1 pad (one of 21, figures), and a 1-2 pad (another nearest one of 21 in horizontal direction, figures) closest to the 1-1 pad (one of 21, figures) along the horizontal direction (horizontal direction, figures),
wherein the second pad (11, [26]) includes a 2-1 pad (one of 11, figures), and a 2-2 pad (another nearest one of 11 in horizontal direction, figures) closest pad to the 2-1 pad (one of 11, figures) along the horizontal direction (horizontal direction, figures), and
wherein a first distance between the 1-2 pad (another nearest one of 21 in horizontal direction, figures) and the 1-2 pad (another nearest one of 21 in horizontal direction, figures) along the horizontal direction (horizontal direction, figures) is smaller than a second distance between the 2-1 pad (one of 11, figures) and the 2-2 pad (another nearest one of 11 in horizontal direction, figures) along the horizontal direction (horizontal direction, figures).
Regarding claim 16, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 11 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, an upper surface of the first pad (21, [26]) has a first shape (figures), and an upper surface of the second pad (11, [26]) has a second shape (figures), and wherein the first shape is different from the second shape (figures).
Regarding claim 17, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 11 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, the circuit layer (11/21/22, [26]) is embedded in the insulating layer (12, [26]),
wherein a first stepped portion (step of 20/D2, [37], [45]) is provided between an upper surface of the first pad (21, [26]) and an upper surface of the insulating layer (12, [26]), and
wherein a second stepped portion (step of 20/D1, [37], [45]) is provided between an upper surface of the second pad (11, [26]) and the upper surface of the insulating layer (12, [26]).
Regarding claim 18, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 17 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, a first depth of the first stepped portion (step of 20/D2, [37], [45]) is same with a second depth of the second stepped portion (step of 20/D1, [37], [45]) (figures).
Regarding claim 19, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 17 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, a first depth of the first stepped portion (step of 20/D2, [37], [45]) is different from a depth of the recess (area of depth D2, figures).
Regarding claim 20, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 11 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, a protective layer (19, [26]) disposed on the insulating layer (12, [26]),
wherein the protective layer (19, [26]) includes at least one opening (figures).
Regarding claim 21, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 20 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, the opening (opening of 19, figures) includes a first opening (opening of 19 on 21, figures) that overlaps the first pad (21, [26]) in a vertical direction and a second opening (opening of 19 on 11, figures) that overlaps the second pad (11, [26]) in a vertical direction, and
wherein a width of the first opening (opening of 19 on 21, figures) along the horizontal direction (horizontal direction, figures) is different from a width of the second opening (opening of 19 on 11, figures) along the horizontal direction (horizontal direction, figures).
Regarding claim 22, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 21 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, the width of the first opening (opening of 19 on 21, figures) along the horizontal direction (horizontal direction, figures) is greater than the width of the second opening (opening of 19 on 11, figures) along the horizontal direction (horizontal direction, figures).
Regarding claim 23, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 22 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, the width of the first opening (opening of 19 on 21, figures) along the horizontal direction (horizontal direction, figures) is greater than the first width of the first pad (21, [26]), and
wherein the width of the second opening (opening of 19 on 11, figures) along the horizontal direction (horizontal direction, figures) is smaller than the second width of the second pad (11, [26]).
Regarding claim 24, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 23 as described above.
Kaneko020 in view of Kaneko027 does not explicitly disclose the protective layer includes a first part in contact with an upper surface of the insulating layer and a second part in contact with an upper surface of the second pad, and wherein a lower surface of the first part and a lower surface of the second part have a step.
Kaneko020 teaches, in at least figures 11A-11B and related text, the device comprising the protective layer (19, [154]) includes a first part in contact with an upper surface of the insulating layer (12, [154]) and a second part in contact with an upper surface of the second pad (11, [154]), and wherein a lower surface of the first part and a lower surface of the second part have a step (figures), for the purpose of providing pads which can enhance the reliability of connections with connection targets ([8]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Kaneko020 in view of Kaneko027 to have the protective layer including a first part in contact with an upper surface of the insulating layer and a second part in contact with an upper surface of the second pad, and wherein a lower surface of the first part and a lower surface of the second part have a step, as taught by figures 11A-11B of Kaneko020, for the purpose of providing pads which can enhance the reliability of connections with connection targets ([8], Kaneko020).
Regarding claim 26, Kaneko020 in view of Kaneko027 discloses the circuit board of claim 11 as described above.
Kaneko020 further discloses, in at least figures 1A-2 and related text, a width of the recess (area of depth D2, figures) along the horizontal direction (horizontal direction, figures) satisfies a range of 30% to 90% of the first width (width of 21 with thickness (T2 and D2) before recessing, [37], figures).
Regarding claim 27, Kaneko020 discloses, in at least figures 1A-2 and related text, a semiconductor comprising:
an insulating layer (12, [26]); and
a circuit layer (11/21/22, [26]) disposed on the insulating layer (12, [26]), wherein the circuit layer (11/21/22, [26]) includes a first pad (21, [26]) having a first width (width of 21, figures) along a horizontal direction (horizontal direction, figures), and a second pad (11, [26]) having a second width (width of 11, figures) along the horizontal direction (horizontal direction, figures), and a trace (22, [26]) having a third width (width of 22, figure 2) along the horizontal direction (horizontal direction, figures),
wherein the second width (width of 11, figures) is greater than the first width (width of 21, figures),
wherein the first width (width of 21, figures) is greater than the third width (width of 22, figure 2),
wherein the first pad (21, [26]) includes a recess (area of depth D2, figures) provided on an upper surface (upper surface of 21, figures) thereof.
Kaneko020 does not explicitly disclose a semiconductor device disposed on the circuit layer; a third stepped portion is provided between an upper surface of the trace and an upper surface of the insulating layer.
Kaneko020 teaches, in at least figures 7A-7C and related text, the device comprising a semiconductor device (101/102, [110]) disposed on the circuit layer (11/21/22, [109]), for the purpose of providing pads which can enhance the reliability of connections with connection targets ([8]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in figures 1A-2 of Kaneko020 to have the semiconductor device disposed on the circuit layer, as taught by figures 7A-7C of Kaneko020, for the purpose of providing pads which can enhance the reliability of connections with connection targets ([8], Kaneko020).
Kaneko027 teaches, in at least figures 1A-1C and related text, the device comprising a third stepped portion is provided between an upper surface of the trace (21, [21]) and an upper surface of the insulating layer (12, [21]), for the purpose of providing a wiring board, etc. having pads which can enhance the reliability of connections with connection targets ([8]).
Kaneko020 and Kaneko027 are analogous art because they both are directed to circuit board and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kaneko020 with the specified features of Kaneko027 because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Kaneko020 to have the third stepped portion being provided between an upper surface of the trace and an upper surface of the insulating layer, as taught by Kaneko027, for the purpose of providing a wiring board, etc. having pads which can enhance the reliability of connections with connection targets ([8], Kaneko027).
Regarding claim 28, Kaneko020 in view of Kaneko027 discloses the semiconductor of claim 27 as described above.
Kaneko020 further teaches, in at least figures 1A-2, 7A-7C and related text, a connection part (101a/102b, [110], [111]) disposed on the first pad (21, [109], [110]), wherein the connection part (101a/102b, [110], [111]) is disposed in the recess (area of depth D2, figures), for the purpose of providing pads which can enhance the reliability of connections with connection targets ([8]).
Allowable Subject Matter
Claims 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 11 and 14 that recite "the trace is disposed between the 1-1 pad and the 1-2 pad" in combination with other elements of the base claims 11 and 14.
Claims 29-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 27 and 29 that recite "the trace is disposed between the 1-1 pad and the 1-2 pad" in combination with other elements of the base claims 27 and 29.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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