DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1, 3-5, and 8-9 filed on 7/23/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 10-15 have been considered. Claim(s) 2, and 7 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 5-8, filed 05/08/2026, with respect to the rejection(s) of claim(s) 1-15 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of COOPER.
Regarding Claim 1. Applicant argues that HUERNER, either alone or in combination of OKUMURA, fails to disclose or suggest the amended features to claim 1, recites, “wherein the source region has a form of an interdigitated finger structure…comprises a stripe and a plurality of fingers…via the stripe on one end…wherein the well layers is located…interdigitated finger structure.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of COOPER teaches a semiconductor structure (Fig. 1, 10, semiconductor device), comprising: wherein the well layer (annotated Figure 1) comprises a well region (Fig. 1, 26/28, the wells) separating the source region (Fig. 1, 46/48) from the drift layer (Fig. 1, 14) and a well contact region (Fig. 1, 42/44, the base contact regions) at the first main surface (annotated Figure 1) which has a higher maximum doping concentration (Fig. 1, “p+” concentration, [0029]) than the well region (Fig. 1, “p” concentration, [0023]), and
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wherein the source region (Fig. 3, 154/156) has a form of an interdigitated finger structure (annotated Figure 3) with the well contact region (Fig. 3, 158/160, the base contact regions), wherein the interdigitated finger structure (annotated Figure 3) comprises a stripe (Figs. 3/4, the strips, [0034]) and a plurality of fingers (annotated Figure 3) that are each connected to each other via the stripe (Fig. 3, the strips, [0034]) on one end and not connected to each other on a second end that is opposite the first end, and wherein the well layer (Fig. 3, 158/160, the base contact regions with the wells as in annotated Figure 1 above) is located between fingers (annotated Figure 3) of the interdigitated finger structure (annotated Figure 3).
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Regarding Claims 3-6, and 8-15: The dependent claims 3-6, and 8-15 follow similar arguments as claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claim 1 is indefinite because the stripe, element 33 as pointed in the source region, 20 (see Figures 2B-2H) is unclear with respect to the specification paragraphs, [0028] and [0053]. Due to the lack of structure of the stripe, 33, the claim 1 renders indefinite and further leads to broadest reasonable interpretation.
Claims 3-6, and 8-15 depends on Claim 1 follows the similar arguments as above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-6, 8-9, and 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Andreas Huerner et al, (hereinafter HUERNER), US 20190393299 A1, in view of Keiji Okumura, (hereinafter OKUMURA), US 20200152748 A1, and James Cooper et al, (hereinafter COOPER), US 20060192256 A1.
Regarding Claim 1, HUERNER teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), comprising:
a semiconductor body (Fig. 5B, 100, silicon carbide body) which includes a first main surface (Fig. 5B, 101, first surface) and a second main surface (Fig. 5B, 102, second surface),
a gate insulator (Fig. 5B, 159, gate dielectric) arranged at the first main surface (Fig. 5B, 101, first surface), and
a gate electrode (Fig. 5B, 155) separated from the semiconductor body (Fig. 5B, 100, silicon carbide body) by the gate insulator (Fig. 5B, 159, gate dielectric), wherein the semiconductor body (Fig. 5B, 100, silicon carbide body) comprises
a drift layer (Fig. 5B, 130/131, drift structure/drift zone) of a first conductivity type (Fig. 5B, n-type, [0075]),
a well layer (Figs. 3/5B, 120, body region) of a second conductivity type (Figs. 3/5B, p-type, [0080]) being different from the first conductivity type (Fig. 5B, n-type, [0075]) and forming a first junction (annotated Figure 5B) to the drift layer (Fig. 5B, 130/131, drift structure/drift zone),
a source region (Fig. 5B, 110, [0084]) of the first conductivity type (Fig. 5B, n-type, [0084]) forming a second junction (annotated Figure 5B) to the well layer (Figs. 3/5B, 120, body region), and
an island region (Fig. 5B, 170/171, auxiliary region/auxiliary portions) of the second conductivity type (Fig. 5B, p-type), wherein attaching the source region (Fig. 5B, 110, [0084]) such that the source region (Fig. 5B, 110, [0084]) separates the island region (Fig. 5B, 170/171, auxiliary region/auxiliary portions) from the well layer (Figs. 3/5B, 120, body region) in at least 50 % of an island surface area (annotated Figure 5B) of the island region (Fig. 5B, 170/171, auxiliary region/auxiliary portions) in the semiconductor body (Fig. 5B, 100, silicon carbide body),
wherein the island region (Figs. 5A/5B, 170/171, auxiliary region/auxiliary portions) is completely surrounded ([0092]) by the source region (Figs. 5A/5B, N1/110/113, source portions/source region/third portions, [0094], [0101]) in two dimensions (Fig. 5A) of the island region (Figs. 5A/5B, 170, auxiliary region), the two dimensions being parallel (Fig. 5A) to the first main surface (Fig. 5B, 101, first surface).
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Though HUERNER teaches the disconnected island regions (170/171) that are electrically floating ([0092]), HUERNER does not explicitly disclose a power semiconductor device, comprising: wherein the island region is completely surrounded by the source region in two dimensions of the island region.
OKUMURA teaches the power semiconductor device (Fig. 2, semiconductor device, [0047]), wherein the island region (Fig. 2, 14a/4, first portion/p-type base region, [0053]) is completely surrounded (Fig. 4, [0055]) by the source region (Figs. 1/3, n+ -type source region, [0052]) in two dimensions (Figs. 3/5, plan view of a layout, [0028]) of the island region (Fig. 2, 14a/4, first portion/p-type base region, [0053).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUERNER to incorporate the teachings of OKUMURA, such that a power semiconductor device, comprising: wherein the island region is completely surrounded by the source region in two dimensions of the island region, so that a structure in which the ON resistance is reduced, the current between the drain and the source during a short circuit is reduced, generated heat of the semiconductor device is suppressed, and thus the short circuit capability may be increased for the power semiconductor device (OKUMURA, Fig. 16, [0045]).
HUERNER in view of OKUMURA does not explicitly disclose a power semiconductor device, comprising: wherein the well layer comprises a well region separating the source region from the drift layer and a well contact region at the first main surface which has a higher maximum doping concentration than the well region, and wherein the source region has a form of an interdigitated finger structure with the well contact region, wherein the interdigitated finger structure comprises a stripe and a plurality of fingers that are each connected to each other via the stripe on one end and not connected to each other on a second end that is opposite the first end, and wherein the well layer is located between fingers of the interdigitated finger structure.
COOPER teaches a semiconductor structure (Fig. 1, 10, semiconductor device), comprising: wherein the well layer (annotated Figure 1) comprises a well region (Fig. 1, 26/28, the wells) separating the source region (Fig. 1, 46/48) from the drift layer (Fig. 1, 14) and a well contact region (Fig. 1, 42/44, the base contact regions) at the first main surface (annotated Figure 1) which has a higher maximum doping concentration (Fig. 1, “p+” concentration, [0029]) than the well region (Fig. 1, “p” concentration, [0023]), and
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wherein the source region (Fig. 3, 154/156) has a form of an interdigitated finger structure (annotated Figure 3) with the well contact region (Fig. 3, 158/160, the base contact regions), wherein the interdigitated finger structure (annotated Figure 3) comprises a stripe (Figs. 3/4, the strips, [0034]) and a plurality of fingers (annotated Figure 3) that are each connected to each other via the stripe (Fig. 3, the strips, [0034]) on one end and not connected to each other on a second end that is opposite the first end, and wherein the well layer (Fig. 3, 158/160, the base contact regions with the wells as in annotated Figure 1 above) is located between fingers (annotated Figure 3) of the interdigitated finger structure (annotated Figure 3).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUERNER as modified by OKUMURA to incorporate the teachings of COOPER, such that a power semiconductor device, comprising: wherein the well layer comprises a well region separating the source region from the drift layer and a well contact region at the first main surface which has a higher maximum doping concentration than the well region, and wherein the source region has a form of an interdigitated finger structure with the well contact region, wherein the interdigitated finger structure comprises a stripe and a plurality of fingers that are each connected to each other via the stripe on one end and not connected to each other on a second end that is opposite the first end, and wherein the well layer is located between fingers of the interdigitated finger structure. The aforementioned arrangement of the source regions, 154, 156 spaced between each base contact regions, 158, 160 does not substantially increase the on-resistance, the efficiency of the semiconductor device may be improved (COOPER, [0003], [0033]).
Regarding Claim 3, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
OKUMURA further teaches the power semiconductor device (Fig. 2, semiconductor device, [0047]), wherein a distance of the island region (Fig. 2, 14a/4, first portion/p-type base region, [0053]) to the well contact region (Fig. 2, 6, fourth semiconductor region/p++-type contact region, [0047]) is larger than 0.05 µm (Fig. 2, the thickness of the first portion (14a) of the second semiconductor region is in the range from 0.05 µm to 0.25 µm, [0019]).
Regarding Claim 4, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
OKUMURA further teaches the power semiconductor device (Fig. 2, semiconductor device, [0047]), wherein the power semiconductor device (Fig. 2, semiconductor device, [0047]) comprises a source electrode (Fig. 1, 12) arranged at least at a part of the source region (Figs. 1/3, n+ -type source region, [0052]) and at least at a part of the well contact region (Fig. 2, 6, fourth semiconductor region/p++-type contact region, [0047]), wherein the source electrode (Fig. 1, 12) forms an ohmic contact to the source region (Figs. 1/3, n+ -type source region, [0052]) and to the well contact region (Fig. 2, 6, fourth semiconductor region/p++-type contact region, [0047]).
HUERNER further teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), wherein the source electrode (Fig. 5B, 310, first load electrode) is free from an ohmic contact (the auxiliary region, 170 may float, [0092]) to the island region (Fig. 5B, 170/171, auxiliary region/auxiliary portions, [0092]).
Regarding Claim 5, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
OKUMURA further teaches the power semiconductor device (Fig. 2, semiconductor device, [0047]), wherein the power semiconductor device (Fig. 2, semiconductor device, [0047]) comprises a source electrode (Fig. 1, 12) arranged at least at a part of the source region (Figs. 1/3, n+ -type source region, [0052]) and at least at a part of the well layer (Fig. 2, 6/14b, fourth semiconductor region/p++-type contact region/second portion, [0047]) and at least at a part of the island region (Fig. 2, 14a/4, first portion/p-type base region, [0053]), and wherein the source electrode (Fig. 1, 12) forms an ohmic contact (Fig. 2, [0063]) to the source region (Figs. 1/3, n+ -type source region, [0052]) and to the well layer (Fig. 2, 6/14b, fourth semiconductor region/p++-type contact region/second portion, [0047]) and to the island region (Fig. 2, 14a/4, first portion/p-type base region, [0053]).
Regarding Claim 6, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim l.
HUERNER further teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), wherein the island region (Fig. 5B, 170/171, auxiliary region/auxiliary portions) is free from a conducting contact (Fig. 5B, the auxiliary region, 170 may float, [0092]) to the drift layer (Fig. 5B, 130/131, drift structure/drift zone) via a semiconductor region (Fig. 5B, 100, silicon carbide body) and is free from a conducting contact (Fig. 5B, the auxiliary region, 170 may float, [0092]) to the well layer (Figs. 3/5B, 120, body region) via a semiconductor region (Fig. 5B, 100, silicon carbide body).
Regarding Claim 8, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
OKUMURA further teaches the power semiconductor device (Fig. 2, semiconductor device, [0047]), wherein the island region (Fig. 2, 14a/4, first portion/p-type base region, [0053]) is located in a finger of the interdigitated finger structure (Fig. 3, plan view layout is viewed from a front side of the semiconductor substrate, [0028], [0061]) at the first main surface (front surface, [0047]).
Regarding Claim 9, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
OKUMURA further teaches the power semiconductor device (Fig. 2, semiconductor device, [0047]), wherein the source region (Figs. 1/3, n+ -type source region, [0052]) comprises a stripe (Fig. 3, [0060]), wherein the fingers of the interdigitated finger structure (Fig. 3, plan view layout is viewed from a front side of the semiconductor substrate, [0028], [0061]) are connected to the stripe in a connection area (Fig. 3, [0060]), and wherein the island region (Fig. 2, 14a/4, first portion/p-type base region, [0053]) is located in the stripe in the connection area (Fig. 3, [0060]) at the first main surface (front surface, [0047]).
Regarding Claim 11, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
HUERNER further teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), wherein the island region (Figs. 5A/5B, 170/171, auxiliary region/auxiliary portions) is formed as a one of a group comprising a rectangle (annotated Figure 5B), a trapezoid, a hexagon, a circle and an ellipsoid in a plane (Fig. 5B, <11-20>, [0096]) parallel to the first main surface (Fig. 5B, 101, first surface).
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Regarding Claim 12, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
HUERNER further teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), wherein at least one of:
the semiconductor body (Fig. 5B, 100, silicon carbide body) is of a wide bandgap material or of silicon carbide or of silicon (Fig. 5B, 100, [0096]), or
the power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]) is a field-effect transistor or an insulated gate bipolar transistor ([0005], [0024-0025]).
Regarding Claim 13, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
HUERNER further teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), wherein a thickness (annotated Figure 5B) of the island region (Figs. 5A/5B, 170/171, auxiliary region/auxiliary portions) is less than 95% of a thickness (annotated Figure 5B) of the source region (Fig. 5B, 110, [0084]).
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Regarding Claim 14, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
HUERNER further teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), wherein the semiconductor body (Fig. 5B, 100, silicon carbide body) includes a number of island regions (Fig. 5A, 171, auxiliary portions).
Regarding Claim 15, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
HUERNER further teaches a power semiconductor device (Fig. 5B, 500, SiC device, may be a vertical power semiconductor device, [0063]), wherein an island region (Figs. 5A/5B, 170/171, auxiliary region/auxiliary portions) length (annotated Figure 5B) of the island region (Figs. 5A/5B, 170/171, auxiliary region/auxiliary portions) has a value in a range between 5 % and 95 % (annotated Figure 5B) of a source region (Fig. 5B, 110, [0084]) length (annotated Figure 5B) of the source region (Fig. 5B, 110, [0084]).
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Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUERNER, in view of OKUMURA and COOPER as applied to claims 1, 3-6, 8-9, 11-15, and further in view of Florin Udrea, (hereinafter UDREA), US 20060261443 A1.
Regarding Claim 10, HUERNER as modified by OKUMURA and COOPER teaches the power semiconductor device of claim 1.
HUERNER as modified by OKUMURA and COOPER does not explicitly disclose the power semiconductor device, wherein a maximum doping concentration of the island region is in a range between 0.5 1018 cm-3 and 2 1021 cm-3.
UDREA teaches the power semiconductor device (Fig. 1, 1, LIGBT, lateral insulated gate bipolar transistor device), wherein a maximum doping concentration of the island region (Fig. 1, 9, n+ floating islands) is in a range between 0.5 1018 cm-3 and 2 1021 cm-3 (the n+ islands, 9 are highly doped, for example in the range of 1019 cm-3 to 1021 cm-3, [0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUERNER as modified by OKUMURA and COOPER to incorporate the teachings of UDREA, such that the power semiconductor device, wherein a maximum doping concentration of the island region is in a range between 0.5 1018 cm-3 and 2 1021 cm-3, so that the highly doped island regions built up in the lowly-dope drift region or layer, leading to a sharp increase in the electrical conductivity of the drift layer (UDREA, [0008]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20080251838 A1 – Figure 9
STATEMENT OF RELEVANCE – A plane shape of a gate electrode, 29 is divided into two parts and each part is formed so as to have a stripe pattern similar to the plane shape of the gate electrode of a conventional power MOSFET.
US 20110291110 A1 – Figure 5F
STATEMENT OF RELEVANCE – The p-type deep layer, 10 and the current diffusion layer, 2a are alternatively arranged in an interdigitated finger-like structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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