Prosecution Insights
Last updated: July 17, 2026
Application No. 18/290,995

DISPLAY DEVICE

Non-Final OA §102
Filed
Jan 22, 2024
Priority
Jul 21, 2021 — nonprovisional of PCTKR2021009371
Examiner
CUTLER, ETHAN EDWARD
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Electronics Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
12m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
50 granted / 55 resolved
+22.9% vs TC avg
Moderate +13% lift
Without
With
+13.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
19 currently pending
Career history
76
Total Applications
across all art units

Statute-Specific Performance

§103
92.2%
+52.2% vs TC avg
§102
5.9%
-34.1% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 55 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the title include the phrase “including a light emitting device with three distinct semiconductor layers.” Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20150333102 A1 to Sato et al. (hereinafter “Sato”). Regarding claim 20, Sato teaches a display device (fig. 17), comprising: a substrate (101; fig. 17) [0039]; a barrier rib (insulating layer 103; fig. 17) [0039] having an assembly hole (103a; fig. 7A) [0039] on the substrate (101); a semiconductor light emitting device (106; figs. 7B & 17) [0039] in the assembly hole (103a); and a first connection part (color conversion layer 105; figs. 7D & 17) [0040] comprising a first region (region of 105) disposed in the assembly hole (103a) and a second region (lateral region of 105 in fig. 17) on an upper surface (vertically upper) of the barrier rib (103) and electrically connected to a side surface (horizontal side) of the semiconductor light emitting device (106); and a first wiring electrode (through electrode 104a; fig. 17) [0048] electrically connected to the second region (lateral regions) of the first connection part (105). Allowable Subject Matter 5. Claims 1-19 are allowed. The following is an examiner’s statement of reasons for allowance. The claims are allowable at least because the independent claims are amended to include allowable subject matter. In specific, regarding claim 1, the claim recites the limitations “a first conductivity type semiconductor layer comprising a first-first conductivity type semiconductor laver and a first-second conductivity type semiconductor layer on the first-first conductivity type semiconductor layer; an active layer on the first-second conductivity type semiconductor layer; a second conductive semiconductor layer on the active layer.” These limitations, considered in conjunction with “a display device, comprising: a substrate; a barrier rib having an assembly hole on the substrate; a semiconductor light emitting device in the assembly hole; and a first connection part disposed in the assembly hole and on the barrier rib and electrically connected to a side surface of the semiconductor light emitting device wherein the semiconductor light emitting device comprises; a protective layer, wherein the first-first conductivity type semiconductor layer comprises: a first region having an area equal to that of the first-second conductivity type semiconductor layer; and a second region surrounding the first region and, wherein the protective laver surrounds a side surface of the first-second conductivity type semiconductor layer and vertically overlaps with the second region of the first-first conductivity type semiconductor layer,” comprise the allowable subject matter. Regarding the allowable subject matter, there are many references which employ a first semiconductor and a second semiconductor layer with an active layer disposed therebetween i.e., forming a p-n junction and a p-n diode, but there is not found a reference which would reasonably read on a light emitting device with an additional semiconductor layer (of opposite doping type to the first-second type semiconductor layer) as to read on claim 1. Moreover, the positional relationship of each semiconductor layer makes the interpretation narrower. In specific, the term “on” i.e., being in contact with, being used for the positioning of each of the first-first, first-second, second, and active layers. While these layers may switch positions in some ways, the interpretation is narrower because of these positional terms. The closest art which would read on claim 1 would be US 20220254961 A1 or US 20220320057 A1 which both read on claim 1 save for the first-first type semiconductor layer and subsequent positioning. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ETHAN EDWARD CUTLER/Examiner, Art Unit 2892 /NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Jan 22, 2024
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+13.2%)
3y 5m (~12m remaining)
Median Time to Grant
Low
PTA Risk
Based on 55 resolved cases by this examiner. Grant probability derived from career allowance rate.

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