Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2, 4, 8 and 9 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kandekar et al. (US 10,804,233).
Regarding claim 4, Kandekar et al. disclose a package body (100, package assembly) [col. 3 lines 29-30] including a semiconductor chip (102)[col. 3 lines 30-50] and having a plurality of first lands (112 bonding pads) arranged on one surface; and a plurality of solder bumps that are individually bonded to the plurality of lands[ cols. 3-4], respectively, wherein the plurality of solder bumps (116,118) include core solder bumps (118) including cores and coreless solder bumps without cores (116)[col. 4 lines 12-42](fig. 1A) wherein the core solder bumps (118) are arranged in a location superimposed on a contour of the semiconductor chip in plan view (fig. 1c the examiner considers the edge “a countour” of the semiconductor chip ).
Regarding claim 2, Kandekar et al. disclose the core solder bumps are arranged at sections where stress caused by a difference in thermal expansion coefficient between the package body and a mounting substrate are concentrated during a cooling process performed after each of the plurality of solder bumps including the core solder bumps and the coreless solder bumps is melted and individually bonded to each of a plurality of second lands on the mounting substrate (fig. 1A and 1C).
Regarding claim 8, Kandekar et al. disclose the core solder bumps include the cores (120) and solder layers (122) covering the cores, and the coreless solder bumps are composed of solder [col. 4 lines 27-42].
Regarding claim 9, Kandekar et al. disclose the core solder bumps and the coreless solder bumps have an identical external shape (fig. 1A).
Claim(s) 5, 19-21 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kandekar et al. (US 10,804,233).
Regarding claim 5, Kandekar et al. disclose a package body (100, package assembly) [col. 3 lines 29-30] including a semiconductor chip (102)[col. 3 lines 30-50] and having a plurality of first lands (112 bonding pads) arranged on one surface; and a plurality of solder bumps that are individually bonded to the plurality of lands[ cols. 3-4], respectively, wherein the plurality of solder bumps (116,118) include core solder bumps (118) including cores and coreless solder bumps without cores (116)[col. 4 lines 12-42](fig. 1A) the core solder bumps are arranged at a corner of the package body and in a location superimposed on a contour of the semiconductor chip in plan view(fig. 1c)( the examiner considers the edge “a countour” of the semiconductor chip).
Regarding claim 19, Kandekar et al. disclose the core solder bumps are arranged at sections where stress caused by a difference in thermal expansion coefficient between the package body and a mounting substrate are concentrated during a cooling process performed after each of the plurality of solder bumps including the core solder bumps and the coreless solder bumps is melted and individually bonded to each of a plurality of second lands on the mounting substrate (fig. 1A and 1C).
Regarding claim 20, Kandekar et al. disclose the core solder bumps include the cores (120) and solder layers (122) covering the cores, and the coreless solder bumps are composed of solder [col. 4 lines 27-42].
Regarding claim 21, Kandekar et al. disclose the core solder bumps and the coreless solder bumps have an identical external shape (fig. 1A).
Claim(s) 11, 13, 17 and 18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kandekar et al. (US 10,804,233).
Regarding claim 13, Kandekar et al. disclose a semiconductor device having a plurality of first lands (112) arranged on one surface of a package body including a semiconductor chip(fig 1a) ;a mounting substrate having a plurality of second lands (121)(fig. 1A) arranged on one surface; and a plurality of solder bumps that are individually interposed between the plurality of first lands and the plurality of second lands (fig. 1B), respectively, and are individually bonded to the plurality of first lands and the plurality of second lands, respectively, wherein the plurality of solder bumps include core (118) solder bumps including cores and coreless solder bumps (116) without cores wherein the core solder bumps (118) are arranged in a location superimposed on a contour of the semiconductor chip in plan view (fig. 1c the examiner considers the edge “a countour” of the semiconductor chip ).
Regarding claim 11, Kandekar et al. disclose the core solder bumps are arranged at sections where stress caused by a difference in thermal expansion coefficient between the package body and a mounting substrate are concentrated during a cooling process performed after each of the plurality of solder bumps including the core solder bumps and the coreless solder bumps is melted and individually bonded to each of a plurality of second lands on the mounting substrate (figs. 1A , 1B and 1C).
Regarding claim 17, Kandekar et al. disclose the core solder bumps include the cores (120) and solder layers (122) covering the cores, and the coreless solder bumps are composed of solder [col. 4 lines 27-42].
Regarding claim 18, Kandekar et al. disclose the core solder bumps and the coreless solder bumps have an identical external shape (fig. 1A).
Claim(s) 14 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kandekar et al. (US 10,804,233).
Regarding claim 13, Kandekar et al. disclose a semiconductor device having a plurality of first lands (112) arranged on one surface of a package body including a semiconductor chip(fig 1a) ;a mounting substrate having a plurality of second lands (121)(fig. 1A) arranged on one surface; and a plurality of solder bumps that are individually interposed between the plurality of first lands and the plurality of second lands (fig. 1B), respectively, and are individually bonded to the plurality of first lands and the plurality of second lands, respectively, wherein the plurality of solder bumps include core (118) solder bumps including cores and coreless solder bumps (116) without cores wherein the core solder bumps are arranged at a corner of the package body and in a location superimposed on a contour of the semiconductor chip in plan view(fig. 1c)( the examiner considers the edge “a countour” of the semiconductor chip).
Allowable Subject Matter
Claims 6-7, 15-16 and 22-24 are allowable.
The following is a statement of reasons for the indication of allowable subject matter: a package body including a semiconductor chip and having a plurality of first lands arranged on one surface; and a plurality of solder bumps that are individually bonded to the plurality of lands, respectively, wherein the plurality of solder bumps include core solder bumps including cores and coreless solder bumps without cores wherein the package body includes a plurality of the semiconductor chips arranged in a two-dimensional plane, and the core solder bumps are arranged between the semiconductor chips adjacent to each other in plan view (claims 6-7 and 22-24) a semiconductor device having a plurality of first lands arranged on one surface of a package body including a semiconductor chip; a mounting substrate having a plurality of second lands arranged on one surface; and a plurality of solder bumps that are individually interposed between the plurality of first lands and the plurality of second lands, respectively, and are individually bonded to the plurality of first lands and the plurality of second lands, respectively, wherein the plurality of solder bumps include core solder bumps including cores and coreless solder bumps without cores wherein the plurality of solder bumps include core solder bumps including cores and coreless solder bumps without cores wherein the package body includes a plurality of the semiconductor chips arranged in a two-dimensional plane, and wherein the core solder bumps are arranged between the semiconductor chips adjacent to each other in plan view. (claims 15-16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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