DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 23, 2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: PACKAGE ON PACKAGE SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF REINFORCED THROUGH ELECTRODES.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2014/0374894 A1) in view of Sato (US 2015/0091118 A1).
Claim 1, Chen discloses a semiconductor package (package on package structure 100b is a semiconductor package, hereinafter, semiconductor package 100b, [0045], Fig. 11) comprising:
a first insulating layer (first solder mask 214 serves as an insulating layer, hereinafter, first insulating layer 214, [0025], Fig. 4);
a first circuit pattern (circuit base 211 and first electrically conductive pattern 212 form a circuit pattern, hereinafter, first circuit pattern 211/212, [0026], Fig. 4) disposed on the first insulating layer 214 (first circuit pattern 211/212 is disposed on the first insulating layer 214, [0026], Fig. 4) and including a first pad (first circuit pattern 211/212 includes the first electrically conductive pattern layer 2112, hereinafter, first pad 2112, [0026], Fig. 4);
a first molding layer (epoxy molding compound layer 30a is a first molding layer, hereinafter, first molding layer 30a, [0035], Fig. 6) disposed on an upper surface of the first insulating layer 214 (first molding layer 30a is disposed on an upper surface of the first insulating layer 214, [0035], Fig. 6);
a through electrode (first solder pad 2121, electrically conductive posts 13, electrically conductive block 33b, and solder balls 51 are a through electrode, hereinafter, through electrode 2121/13/33b/51, [0046], Fig. 11) including a first conductive coupling part 2121 disposed on the first pad 2112 (through electrode 2121/13/33b/51 includes first solder pad 2121 which is a first conductive coupling part 2121, hereinafter, first conductive coupling part 2121 disposed on the first pad 2112, [0046], Fig. 11) and having a first width (first conductive coupling part 2121 has a first width W1, [0046], Fig. 11) and a through part (electrically conductive posts 13 is a through part, hereinafter, through part 13, [0046], Fig. 11) disposed on the first conductive coupling part 2121 (through part 13 is disposed on the first conductive coupling part 2121, [0046], Fig. 11) and having a second width smaller than the first width W1 (through part 13 has a second width W2 smaller than the first width W1, [0046], Fig. 11), and passing through of the first molding layer 30a (through part 13 passes through of the first molding layer 30a, [0046], Fig. 11); and
a second conductive coupling part (solder balls 51 is a second conductive coupling part, hereinafter, second conductive coupling part 51, [0046], Fig. 11) disposed on the through part 13 of the through electrode 2121/13/33b/51 (second conductive coupling part 51 is disposed on the through part 13 of the through electrode 2121/13/33b/51, [0046], Fig. 11).
Chen does not explicitly disclose a through electrode including a first conductive coupling part disposed on the first pad and having a first width and a through part disposed on the first conductive coupling part and having a second width smaller than the first width; and a second conductive coupling part disposed on the through part of the through electrode; wherein the first width of the first conductive coupling part is smaller than a third width of the second conductive coupling part.
However, Sato discloses a semiconductor package (Sato, stacked package of microelectronic assemblies 410/488 form a package on package structure, hereinafter, semiconductor package 410/488, [0084], Figs. 6 and 7) comprising:
a first insulating layer (Sato, encapsulation layer 42/442 is an insulating layer, hereinafter, first insulating layer 42/442, [0066] and [0088], Figs. 6 and 7; Chen, first insulating layer 214, [0025], Fig. 4);
a first circuit pattern (Sato, conductive elements 28/428/441/440 are a first circuit pattern, hereinafter, first circuit pattern 28, [0068], Figs. 6 and 7; Chen, first circuit pattern 211/212, [0026], Fig. 4) disposed on the first insulating layer 42/442 (Sato, first circuit pattern 28 is disposed on the first insulating layer 42/442, [0068], Figs. 6 and 7; Chen, first circuit pattern 211/212 is disposed on the first insulating layer 214, [0026], Fig. 4) and including a first pad (Sato, first circuit pattern 28 includes base 434 which is a first pad, hereinafter, first pad 434, [0068], Figs. 6 and 7; Chen, first pad 2112, [0026], Fig. 4);
a first molding layer (Sato, substrate 12/412 may include molding materials and is a first molding layer, hereinafter, first molding layer 12/412, [0085], Figs. 6 and 7; Chen, first molding layer 30a, [0035], Fig. 6) disposed on an upper surface of the first insulating layer 42/442 (Sato, first molding layer 12/412 is disposed on an upper surface of the first insulating layer 42/442, [0085], Figs. 6 and 7; Chen, first molding layer 30a is disposed on an upper surface of the first insulating layer 214, [0035], Fig. 6);
a through electrode (Sato, through electrode 32/432/428/441/440/452, [0085], Figs. 6 and 7; Chen, through electrode 2121/13/33b/51, [0046], Fig. 11) including a first conductive coupling part (Sato, conductive elements 428 are a first conductive coupling part, hereinafter, first conductive coupling part 428, [0087], Figs. 6 and 7; Chen, first conductive coupling part 2121, [0046], Fig. 11) disposed on the first pad (Sato, through electrode 32/432/428/441/440/452 is disposed on the first pad 434, [0085], Fig. 6; Chen, first conductive coupling part 2121 disposed on the first pad 2112, [0046], Fig. 11) and having a first width (Sato, first conductive coupling part 428 has a first width W1, [0087], Figs. 6 and 7; Chen, first conductive coupling part 2121 has a first width W1, [0046], Fig. 11) and a through part (Sato, wire bonds 32/432 are a through part, hereinafter, through part 32/432, [0087], Figs. 6 and 7; Chen, through part 13, [0046], Fig. 11) disposed on the first conductive coupling part 428 (Sato, through part 32/432 is disposed on the first conductive coupling part 428, [0087], Figs. 6 and 7; Chen, through part 13 is disposed on the first conductive coupling part 2121, [0046], Fig. 11) and having a second width smaller than the first width (Sato, through part 32/432 has a second width W2 smaller than the first width W1 (i.e. of the first conductive coupling part 428), [0087], Figs. 6 and 7; Chen, through part 13 has a second width W2 smaller than the first width W1 and passes through of the first molding layer 30a, [0046], Fig. 11); and
a second conductive coupling part (Sato, pad 440 is a second conductive coupling part, hereinafter, second conductive coupling part 440, [0087], Figs. 6 and 7; Chen, second conductive coupling part 51, [0046], Fig. 11) disposed on the through part 32/432 of the through electrode 32/432/428/441/440/452 (Sato, second conductive coupling part 440 is disposed on the through part 32/432 of the through electrode 32/432/428/441/440/452, [0087], Figs. 6 and 7; Chen, second conductive coupling part 51 is disposed on the through part 13 of the through electrode 2121/13/33b/51, [0046], Fig. 11);
wherein the first width of the first conductive coupling part 428 is smaller than a third width of the second conductive coupling part 440 (Sato, first width of the first conductive coupling part 428 is smaller than a third width of the second conductive coupling part 440, Figs. 6 and 7; Chen, first width w1 of the first conductive coupling part 2121 is smaller than a third width w3 of the second conductive coupling part 51, [0046], Fig. 11). The combination to utilize a first conductive coupling part smaller than the second coupling part ensures the probability of generating bubbles in the connection bodies is lowered, and the rate of finished product of the package on package structure is improved (Chen, [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a first conductive coupling part smaller than the second coupling part to ensure the probability of generating bubbles in the connection bodies is lowered, and the rate of finished product of the package on package structure is improved (Chen, [0039]).
Claim 2, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 1.
Chen/Sato discloses wherein the through electrode (Sato, through electrode 32/432/428/441/440/452, [0085], Figs. 6 and 7; Chen, through electrode 2121/13/33b/51, [0046], Fig. 11) includes a reinforcing part (Sato, through electrode 32/432/428/441/440/452 includes sacrificial mass 78 (i.e. solder paste) and solder mass 52 which are a reinforcing part, hereinafter, reinforcing part 52/78, [0087], Figs. 6 and 7; Chen, electrically conductive block 33b is a reinforcing part, hereinafter, reinforcing part 33b, [0046], Fig. 11) disposed between the first conductive coupling part and the through part (Sato, reinforcing part 52/78 is disposed between the first conductive coupling part 440 and the through part 32/432, [0087], Figs. 6, 7, and 17C; Chen, electrically conductive block 33b is a reinforcing part, hereinafter, reinforcing part 33b, [0046], Fig. 11).
Claim 3, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 2.
Chen/Sato discloses wherein the reinforcing part has a fourth width greater than the second width of the through part and smaller than the first width of the first conductive coupling part (Sato, reinforcing part 52/78 has a fourth width greater than the second width of the through part 32/432 and smaller than the first width of the first conductive coupling part 440, [0087], Figs. 6, 7, and 17C; Chen, reinforcing part 33b has a fourth width greater than the second width of the through part 13 and smaller than the first width of the first conductive coupling part 2121, [0046], Fig. 11).
Claim 4, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 2.
Chen/Sato discloses wherein the reinforcing part has a width ranging between 110% and 150% of a width of the through part (Sato, reinforcing part 52/78 has a width ranging between 110% and 150% of a width of the through part 32/432, [0087], Figs. 6 and 7; Chen, reinforcing part 33b has a width ranging between 110% and 150% of a width of the through part 13, [0046], Fig. 11).
Claim 6, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 2.
Chen/Sato discloses wherein the first conductive coupling part, the reinforcing part, and the through part are provided with the same metal material as each other (Sato, first conductive coupling part 428, reinforcing part 52/78, and through part 32/432 are provided with the same metal material as each other, [0018], Figs. 6, 7, and 17C; Chen, first conductive coupling part 2121, reinforcing part 33b, and through part 32/432 may be provided with the same metal material as each other, [0018], Fig. 11), and
wherein a lower surface of the first conductive coupling part is in contact with the first pad (Sato, first coupling part 428 is disposed on the first pad 434, [0085], Fig. 6; Chen, first conductive coupling part 2121 disposed on the first pad 2112, [0046], Fig. 11).
Claim 8, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 7.
Chen/Sato discloses wherein the height of the through electrode is greater than 100 µm (Sato, a height of the through electrode 28 is greater than 100 µm (i.e. 100 µm to 500 µm), [0066], Figs. 6, 7, and 17C; Chen, through electrode 2121/13/33b/51, [0046], Fig. 11), and
wherein a width of the through part is greater than 40 µm (Sato, a width of the through part 32/432 is greater than 40 µm (i.e. 40 µm to 150 µm), [0073], Figs. 6 and 7; Chen, through part 13, [0046], Fig. 11).
Claim 9, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 1.
Chen/Sato discloses wherein a straightness corresponding to an inclined angle of the through part with respect to the virtual vertical line is 10 degrees or less (Sato, a straightness corresponding to an inclined angle of the through part 32/432 with respect to the virtual vertical line is 10 degrees or less, [0087], Figs. 6 and 7; Chen, a straightness corresponding to an inclined angle of the through part 13 with respect to the virtual vertical line is 10 degrees or less, [0046], Fig. 11).
Claim 10, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 2.
Chen/Sato discloses further comprising:
a second insulating layer disposed on an upper surface of the first insulating layer (Chen, first insulation layer 2111 is an insulating layer, hereinafter, second insulating layer 2111 and is disposed on an upper surface of the first insulating layer 214, [0025], Fig. 4; Sato, first insulating layer 42/442, [0066] and [0088], Figs. 6 and 7) and including an opening overlapping an upper surface of the first pad in a vertical direction (Chen, second insulating layer 2111 includes an opening overlapping an upper surface of the first pad 2112 in a vertical direction, [0025], Fig. 4; Sato, first insulating layer 42/442, [0066] and [0088], Figs. 6 and 7); and
wherein the through electrode is disposed on the upper surface of the first pad overlapping the opening of the second insulating layer 2111 in a vertical direction (Chen, through electrode 2121/13/33b/51 is disposed on the upper surface of the first pad 2112 overlapping the opening of the second insulating layer 2111 in a vertical direction, [0046], Fig. 11; Sato, through electrode 32/432/428/441/440/452 and first pad 434, [0068] and, [0085], Figs. 6 and 7).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sato and further in view of Kiso (US 2020/0126897 A1).
Claim 5, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 2.
Chen/Sato does not explicitly disclose wherein an upper surface of the first conductive coupling part includes a concave part concave toward the first pad, and wherein at least a part of the reinforcing part is disposed on the concave part of the first conductive coupling part.
However, Kiso discloses wherein an upper surface of the first conductive coupling part includes a concave part concave toward the first pad (Kiso, an upper surface of the first conductive coupling part 21x includes a concave part concave toward the first pad 11, [0050], Fig. 4C; Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7), and
wherein at least a part of the reinforcing part is disposed on the concave part of the first conductive coupling part (Kiso, at least a part of the reinforcing part 22 is disposed on the concave part of the first conductive coupling part 21x, [0050], Fig. 4C; Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7). The combination to utilize a concave shape in combination with conductive coupling parts ensures the probability of generating bubbles in the connection bodies is lowered, and the rate of finished product of the package on package structure is improved (Chen, [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a concave shape in combination with conductive coupling parts to ensure the probability of generating bubbles in the connection bodies is lowered, and the rate of finished product of the package on package structure is improved (Chen, [0039]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sato and further in view of Chen (US 2020/0411445 A1), hereinafter, Chen*
Claim 7, Chen/Sato discloses the semiconductor package (Chen, semiconductor package 100b, [0045], Fig. 11; Sato, semiconductor package 410/488, [0084], Figs. 6 and 7) of claim 2.
Chen/Sato discloses wherein a height from a lower surface to an upper surface of the through electrode is in the range of 50 µm to 200 µm (Sato, a height from a lower surface 16 to an upper surface 14 of the through electrode 28 is in the range of 50 µm to 200 µm (i.e. 25 µm to 500 µm), [0066], Figs. 6, 7, and 17C; Chen, through electrode 2121/13/33b/51, [0046], Fig. 11), and
Chen/Sato does not explicitly disclose wherein the through part has a width in a range of 10 µm to 100 µm.
However, Chen* discloses wherein the through part has a width in a range of 10 µm to 100 µm (Chen*, through vias 310 may have a width in a range of 10 µm to 100 µm (i.e. 1 µm to 100 µm), [0040], Fig. 2; Sato, through part 32/432, [0087], Figs. 6 and 7; Chen, through part 13, [0046], Fig. 11). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of through via width (result effective at least insofar as through via width yields an improvement in integration density which has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area (Chen*, [0002])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed through via width or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Na (US 2015/0022985 A1) discloses a stacked semiconductor package 500c, further including a plurality of inter-package connectors 230 electrically connected between the lower connecting terminals 312 and the upper connecting terminals 208, and further including a lower molding material 345 (i.e. molding material) in contact with a build-up layer 305 (i.e. of insulating layers) which is in contact with a lower core layer 301 (i.e. insulating layers or epoxy resin).
Mohammad (US 2016/0163639 A1) discloses a package on package structure 10A/10B, further including conductive elements 28 and an encapsulation layer 542 within each package 510.
We (US 2016/0329284 A1) discloses a semiconductor package 100 including a first dielectric layer 122, second dielectric layer 130, further comprising a first plurality of vias 126 and a plurality of die interconnects 168.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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