Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 1, was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments to Rejections of the Non-Final
Applicant's arguments filed on July 1, 2026 regarding the rejections of the Non-Final of April 6, 2026 have been fully considered but they are not persuasive.
Regarding the assertion (response, pgs. 8 and 10) that neither Curtola I nor Umeno involve a regrowth, the Examiner disagrees based on the description of provided in the disclosures. For example, in Curtola I the GaN layers are separately formed ((108) on the substrate or isolation structure, and afterward, separately (116) on the compensation structure; Paragraph [0018]). Examiner notes also that the formation of separate materials necessitates a separate process, regardless of whether the same kind of process is utilized (if grouped as “steps” within a single process vs identified as distinct processes are both within reasonable interpretations regardless).
The claims as presented do not limit the regrowth interface as necessitating any previous formation/deposition method. In the case of the device claims, Applicant would be required to show how the claimed manufacturing method would result in a structurally distinct device over the prior art (See MPEP 2113).
Regarding the assertion (response, pg. 8) that Curtola I doesn’t teach the claimed limitations of a first barrier layer and a second barrier layer, the Applicant is reminded that an ipsissmis verbis test isn't required for anticipation within prior art. The way an author of prior art identifies a structure doesn't change the nature of the elements present. (See MPEP 2131)
Response to Amendments
Applicant’s amendments and arguments related to the amendments as filed July 1, 2026 have been fully considered and are persuasive, the rejection has been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (U.S. Pub. 2013/0043484), hereinafter Curatola I, in view of Makiyama (U.S. Pub. 2019/0207018), hereinafter Makiyama.
Regarding Claim 11, Curatola I teaches a semiconductor assembly ((100); Fig. 1, Paragraph [0018]) comprising:
a first semiconductor growth region (lower layers of (100), below (110); Fig. 1) including:
a first heterostructure configured to form a first two-dimensional electron gas (2DEG) channel ((114); Fig. 1, Paragraph [0019]), the first heterostructure including a first barrier layer (‘barrier 1’ consisting of sublayers (230), (220), and (210) from (110); Figs. 1 and 2, Paragraph [0029]) formed with a first channel layer ((108); Fig. 1, Paragraph [0019]);
a second semiconductor growth region (upper layers of (100), above (110)) formed with the first semiconductor growth region at a regrowth interface (at (110)), the second semiconductor growth region including:
a second heterostructure configured to form a second 2DEG channel ((120); Fig. 1, Paragraph [0020]), the second heterostructure including a second channel layer ((116); Fig. 1, Paragraph [0020]) formed with the first semiconductor growth region;
a second barrier layer (‘barrier 2’ consisting of sublayer (200) from (110); Figs. 1 and 2, Paragraph [0029]) formed with the first barrier layer (‘barrier 1’) at the regrowth interface (at (110)); and first and second spaced apart contact materials ((S) and (D); Fig. 1, Paragraph [0023]) coupled to the second channel layer (116).
Curatola I does not explicitly teach:
- first and second isolation implant regions disposed on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly;
Makiyama teaches a semiconductor assembly (‘HEMT’; Fig. 3C, Paragraph [0035]), comprising:
-first and second isolation implant regions (left and right (3); Fig. 3C, Paragraph [0046]) disposed on opposing lateral sides of the first barrier layer (e.g. (2e) of (2); Figs. 1A and 3C, Paragraph [0038])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Makiyama into the device of Curatola I such that first and second isolation implant regions disposed on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly. This would be due to the fact that doing so would produce the predictable result of reducing leakage current between adjacent HEMTs / electrically isolating the HEMTS.
The limitation “the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly” is necessarily fulfilled by the incorporation of the teachings of Makiyama as the isolation implant regions cover the full sides of the semiconductor stack. Please see also MPEP 2114 (I) regarding functional limitations.
For the following claim rejections, all reference citations are directed towards Curatola I unless otherwise specified. For example, (120) refers to (Curtola I, (120)), while (Makiyama, (2)) refers to element (2) of Makiyama.
Regarding Claim 12, Curatola I as modified by Makiyama teaches the semiconductor assembly ((100); Fig. 1, Paragraph [0018]) of Claim 11, wherein:
-the second barrier layer (‘barrier 2’) has a thickness less than a thickness of the first barrier layer (‘barrier 1’) (See Paragraph [0032]).
Regarding Claim 13, Curatola I as modified by Makiyama teaches the semiconductor assembly ((100); Fig. 1, Paragraph [0018]) of Claim 11, wherein:
- the first barrier layer (‘barrier 1’) includes a first semiconductor material (e.g. AlGaN, Paragraph [0029]), and wherein the second barrier layer (‘barrier 2’) includes a second semiconductor material (e.g. AlGaN, Paragraph [0029]).
Regarding Claim 14, Curatola I as modified by Makiyama teaches the semiconductor assembly ((100); Fig. 1, Paragraph [0018]) of Claim 13, wherein:
- the first and second semiconductor materials include the same semiconductor material (e.g. AlGaN).
Regarding Claim 15, Curatola I as modified by Makiyama teaches the semiconductor assembly ((100); Fig. 1, Paragraph [0018]) of Claim 14, wherein:
- the first and second semiconductor materials include aluminum nitride (both ‘barrier 1’ and ‘barrier 2’ include AlGaN which is an alloy made of AlN and GaN, thus they necessarily include AlN).
Regarding Claim 16, Curatola I as modified by Makiyama teaches the semiconductor assembly ((100); Fig. 1, Paragraph [0018]) of Claim 13, wherein:
-at least one of the first and the second semiconductor materials includes aluminum nitride (both ‘barrier 1’ and ‘barrier 2’ include AlGaN which is an alloy made of AlN and GaN, thus they necessarily include AlN).
Claims 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Umeno et al. (U.S. Pub. 2016/0225889), hereinafter Umeno, in view of Makiyama.
Regarding Claim 17, Umeno teaches a semiconductor assembly ((202); Fig. 28, Paragraph [0297]) comprising:
a first semiconductor growth region (lower layers of (202), below (214); Fig. 28) including:
a first heterostructure configured to form a first two-dimensional electron gas (2DEG) channel ((a0); Fig. 28, Paragraph [0291]), the first heterostructure including a first barrier layer ((214); Fig. 28, Paragraph [0273]) formed with a first channel layer ((213); Fig. 28, Paragraph [0272]);
a second semiconductor growth region (upper layers of (202), above (214); Fig. 28) formed with the first semiconductor growth region at a regrowth interface (at upper surface of (214), the second semiconductor growth region including:
a second heterostructure configured to form a second 2DEG channel ((a); Fig. 28, Paragraph [0301]), the second heterostructure including a second channel layer ((216); Fig. 28, Paragraph [0270]) formed with the first semiconductor growth region;
a buffer layer ((215); Fig. 28, Paragraph [0270]) formed with the first barrier layer (214) at the regrowth interface (at upper surface of (214)); and first and second spaced apart contact materials ((S) and (D); Fig. 28, Paragraph [0300]) coupled to the second channel layer (216).
Umeno does not explicitly teach:
- first and second isolation implant regions disposed on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly;
Makiyama teaches a semiconductor assembly (‘HEMT’; Fig. 3C, Paragraph [0035]), comprising:
-first and second isolation implant regions (left and right (3); Fig. 3C, Paragraph [0046]) disposed on opposing lateral sides of the first barrier layer (e.g. (2e) of (2); Figs. 1A and 3C, Paragraph [0038])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Makiyama into the device of Umeno such that first and second isolation implant regions disposed on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly. This would be due to the fact that doing so would produce the predictable result of reducing leakage current between adjacent HEMTs / electrically isolating the HEMTS.
The limitation “the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly” is necessarily fulfilled by the incorporation of the teachings of Makiyama as the isolation implant regions cover the full sides of the semiconductor stack. Please see also MPEP 2114 (I) regarding functional limitations.
For the following claim rejections, all reference citations are directed towards Umeno unless otherwise specified. For example, (120) refers to (Umeno, (120)), while (Makiyama, (2)) refers to element (2) of Makiyama.
Regarding Claim 18, Umeno as modified by Makiyama teaches a semiconductor assembly ((202); Fig. 28, Paragraph [0297]) of Claim 17, wherein:
-wherein the buffer layer (215) includes a carbon-doped gallium nitride buffer layer (Paragraph [0278]).
Regarding Claim 20, Umeno as modified by Makiyama teaches a semiconductor assembly ((202); Fig. 28, Paragraph [0297]) of Claim 17, wherein:
-the first barrier layer (214) includes aluminum nitride (Paragraph [0273]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Umeno and Makiyama, as applied above, and in further view of Curatola I.
Regarding Claim 19, Umeno as modified by Makiyama teaches a semiconductor assembly ((202); Fig. 28, Paragraph [0297]) of Claim 18, upon which it depends, but neither specifically disclose:
-the buffer layer has a thickness of between about 5 nanometers and about 10 nanometers.
Curatola I teaches a semiconductor assembly ((100); Fig. 1, Paragraph [0018]) formed as an HEMT comprising buffer layer (‘barrier 2’ consisting of sublayer (200) from (110); Figs. 1 and 2, Paragraph [0029]) formed with the first barrier layer (‘barrier 1’ consisting of sublayers (230), (220), and (210) from (110); Figs. 1 and 2, Paragraph [0029]) at the regrowth interface (at (110)), wherein:
-the buffer layer (‘barrier 2’) has a thickness of between about 5 nanometers and about 10 nanometers (e.g. 10 nm, Paragraph [0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Curatola I into the device of Umeno as modified by Makiyama such that the buffer layer has a thickness of between about 5 nanometers and about 10 nanometers. This would be due to the fact that doing so would produce the expected result of incorporating applicable dimensions to ensure device functionality.
Claims 1-6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable by Curatola et al. (U.S. Pub. 2013/0153967), hereinafter Curatola II, in view of Curatola I and Makiyama.
Regarding Claim 1, Curatola II teaches a method (Fig. 4A-4C, Paragraph [0030]) of forming a semiconductor device to reduce or counteract impurities at a regrowth interface, the method comprising:
forming a first semiconductor growth region (As in Fig. 4A), including:
forming a first buffer layer (‘bulk’ layer of (120) as first formed, including bottom surface, excluding where 2DEG will form, see also comparative example with 2DEG shown in Fig. 6A; Fig. 4A, Paragraph [0030]) of a first compound semiconductor material (e.g. GaN, Paragraph [0021]) on a substrate ((100); Fig. 4A, Paragraph [0021]);
forming a first channel layer (e.g. ‘top’ layer of (120) as first formed wherein the 2DEG forms, see also comparative example Fig. 6A) with the first buffer layer (bulk (120));
forming a first barrier layer ((240), subsequentially etched for regrowth and relabeled (140); Figs. 4A-4C, Paragraph [0033]) with the first channel layer (top (120) as first formed) thereby forming a first heterostructure, the first heterostructure configured to form a first two-dimensional electron gas (2DEG) channel (shown as the bottom dashed and dotted line below (220)/(140), Paragraphs [0030] and [0031]; Figs. 4A-4C, See also comparative exampled Fig. 6A); and
forming a second semiconductor growth region (As in Fig. 4B) at the regrowth interface, including:
forming a second heterostructure with the first semiconductor growth region, the second heterostructure configured to form a second 2DEG channel (shown as the top dashed and dotted line below (130), Paragraph [0030]; Figs. 4B-4C) and comprising a second channel layer (e.g. ‘top’ layer of regrowth portion of (120) wherein the second 2DEG forms); and
forming first and second spaced apart contact ((150) and (160); Fig. 4C, Paragraph [0030]) materials coupled to the second channel layer (top of regrowth (120)).
Curatola II’s method does not explicitly disclose:
-reducing or counteracting impurities at the regrowth interface;
Curatola I teaches a semiconductor assembly ((100); Fig. 1, Paragraph [0018]) and associated methods of manufacturing, comprising:
-reducing or counteracting impurities at the regrowth interface (Specifically by incorporation of a plurality of barrier layers, e.g. first barrier layer (‘barrier 1’ consisting of sublayers (230), (220), and (210) from (110); Figs. 1 and 2, Paragraph [0029]) and second barrier layer (‘barrier 2’ consisting of sublayer (200) from (110); Figs. 1 and 2, Paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Curatola I into the method of Curatola II such that it includes a process of reducing or counteracting impurities at the regrowth interface. This would be due to the fact that doing so would increase separation between the upper and lower 2DEGs, thereby lowering forward bias, ensuring stable threshold voltage, and providing high current drive capability (Curatola I, Paragraphs [0006] and [0026]).
Neither Curatola II nor Curatola I explicitly teach:
- forming first and second isolation implant regions on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor device;
Makiyama teaches a method of manufacturing a semiconductor assembly (‘HEMT’; Figs. 1A-3C, Paragraph [0035]), comprising:
-forming first and second isolation implant regions (left and right (3); Fig. 3C, Paragraph [0046]) disposed on opposing lateral sides of the first barrier layer (e.g. (2e) of (2); Figs. 1A and 3C, Paragraph [0038])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Makiyama into the method of Curatola II as modified by Curatola I such that it comprises forming first and second isolation implant regions disposed on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly. This would be due to the fact that doing so would produce the predictable result of reducing leakage current between adjacent HEMTs / electrically isolating the HEMTS.
The limitation “the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly” is necessarily fulfilled by the incorporation of the teachings of Makiyama as the isolation implant regions cover the full sides of the semiconductor stack. Please see also MPEP 2114 (I) regarding functional limitations.
For the following claim rejections, all reference citations are directed towards Curatola II unless otherwise specified. For example, (120) refers to (Curtola II, (120)), while (Makiyama, (2)) refers to element (2) of Makiyama.
Regarding Claim 2, Curatola II as modified by Curatola I and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 1, wherein:
reducing or counteracting impurities at the regrowth interface comprises:
-forming a second barrier layer (Curatola I, ‘barrier 2’) with the first barrier layer (Curatola I, ‘barrier 1’), wherein the second barrier layer has a thickness less than a thickness of the first barrier layer (Curatola I, Paragraph [0032])..
Regarding Claim 3, Curatola II as modified by Curatola I and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 2, wherein:
- the first barrier layer (Curatola I, ‘barrier 1’) includes a first semiconductor material (Curatola I, e.g. AlGaN, Paragraph [0029]), and wherein the second barrier layer (Curatola I, ‘barrier 2’) includes a second semiconductor material (Curatola I, e.g. AlGaN, Paragraph [0029]).
Regarding Claim 4, Curatola II as modified by Curatola I and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 3, wherein:
- the first and second semiconductor materials include the same semiconductor material (Curatola I, e.g. AlGaN).
Regarding Claim 5 Curatola II as modified by Curatola I and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 4, wherein:
- the first and second semiconductor materials include aluminum nitride (Curatola I, both ‘barrier 1’ and ‘barrier 2’ include AlGaN which is an alloy made of AlN and GaN, thus they necessarily include AlN).
Regarding Claim 6, Curatola II as modified by Curatola I and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 3, wherein:
-at least one of the first and the second semiconductor materials includes aluminum nitride (Curatola I, both ‘barrier 1’ and ‘barrier 2’ include AlGaN which is an alloy made of AlN and GaN, thus they necessarily include AlN).
Regarding Claim 10, Curatola II as modified by Curatola I and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 1, wherein:
forming the first buffer layer (Curatola II, first formed bulk (120)) of the first compound semiconductor material on the substrate (Curatola II, (100)) includes:
-forming the first buffer layer (Curatola II, first formed bulk (120)) suprajacent the substrate (Curatola II, (100)) with an intervening layer (Curatola II, (110); Fig. 4A-4C, Paragraph [0021]) formed between the first buffer layer and the substrate.
Claims 1, 7, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable by Curatola II, in view of Umeno and Makiyama.
Regarding Claim 1, Curatola II teaches a method (Fig. 4A-4C, Paragraph [0030]) of forming a semiconductor device to reduce or counteract impurities at a regrowth interface, the method comprising:
forming a first semiconductor growth region (As in Fig. 4A), including:
forming a first buffer layer (‘bulk’ layer of (120) as first formed, including bottom surface, excluding where 2DEG will form, see also comparative example with 2DEG shown in Fig. 6A; Fig. 4A, Paragraph [0030]) of a first compound semiconductor material (e.g. GaN, Paragraph [0021]) on a substrate ((100); Fig. 4A, Paragraph [0021]);
forming a first channel layer (e.g. ‘top’ layer of (120) as first formed wherein the 2DEG forms, see also comparative example Fig. 6A) with the first buffer layer (bulk (120));
forming a first barrier layer ((240), subsequentially etched for regrowth and relabeled (140); Figs. 4A-4C, Paragraph [0033]) with the first channel layer (top (120) as first formed) thereby forming a first heterostructure, the first heterostructure configured to form a first two-dimensional electron gas (2DEG) channel (shown as the bottom dashed and dotted line below (220)/(140), Paragraphs [0030] and [0031]; Figs. 4A-4C, See also comparative exampled Fig. 6A); and
forming a second semiconductor growth region (As in Fig. 4B) at the regrowth interface, including:
forming a second heterostructure with the first semiconductor growth region, the second heterostructure configured to form a second 2DEG channel (shown as the top dashed and dotted line below (130), Paragraph [0030]; Figs. 4B-4C) and comprising a second channel layer (e.g. ‘top’ layer of regrowth portion of (120) wherein the second 2DEG forms); and
forming first and second spaced apart contact ((150) and (160); Fig. 4C, Paragraph [0030]) materials coupled to the second channel layer (top of regrowth (120)).
Curatola II’s method does not explicitly disclose:
-reducing or counteracting impurities at the regrowth interface;
Umeno teaches a semiconductor assembly ((202); Fig. 28, Paragraph [0297]) and associated methods of manufacturing, comprising:
-reducing or counteracting impurities at the regrowth interface (Specifically by incorporation of a second GaN buffer layer ((215); Fig. 28, Paragraph [0270]) which is C-doped (Paragraph [0278]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Umeno into the method of Curatola II such that it includes a process of reducing or counteracting impurities at the regrowth interface. This would be due to the fact that doing so would restrain leakage current (Umeno, Paragraphs [0262], [0278], and [0304]). See also instant Specification which recognizes this technique reduces impurities, Line 30, Pg. 7 – Line 10, Pg. 8; Figs. 3 and 4.
Neither Curatola II nor Umeno explicitly teach:
- forming first and second isolation implant regions on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor device;
Makiyama teaches a method of manufacturing a semiconductor assembly (‘HEMT’; Figs. 1A-3C, Paragraph [0035]), comprising:
-forming first and second isolation implant regions (left and right (3); Fig. 3C, Paragraph [0046]) disposed on opposing lateral sides of the first barrier layer (e.g. (2e) of (2); Figs. 1A and 3C, Paragraph [0038])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Makiyama into the method of Curatola II as modified by Umeno such that it comprises forming first and second isolation implant regions disposed on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly. This would be due to the fact that doing so would produce the predictable result of reducing leakage current between adjacent HEMTs / electrically isolating the HEMTS.
The limitation “the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly” is necessarily fulfilled by the incorporation of the teachings of Makiyama as the isolation implant regions cover the full sides of the semiconductor stack. Please see also MPEP 2114 (I) regarding functional limitations.
For the following claim rejections, all reference citations are directed towards Curatola II unless otherwise specified. For example, (120) refers to (Curtola II, (120)), while (Makiyama, (2)) refers to element (2) of Makiyama.
Regarding Claim 7, Curatola II as modified by Umeno and Makiyama teaches a method (Fig. 4A-4C, Paragraph [0030]) of Claim 1, wherein forming the second buffer layer with the first barrier layer includes:
-forming a second buffer layer (Umeno, (215); Fig. 28, Paragraph [0270]) formed with the first barrier layer (modified Curatola II, (240)/(140)).
Regarding Claim 8, Curatola II as modified by Umeno and Makiyama teaches a method (Fig. 4A-4C, Paragraph [0030]) of Claim 7, wherein forming the second buffer layer with the first barrier layer includes:
forming a carbon-doped gallium nitride buffer layer (Umeno, (215) is C-doped gallium nitride; Paragraph [0278]). with the first barrier layer (modified Curatola II, (240)/(140)).
Regarding Claim 10, Curatola II as modified by Umeno and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 1, wherein:
forming the first buffer layer (Curatola II, first formed bulk (120)) of the first compound semiconductor material on the substrate (Curatola II, (100)) includes:
-forming the first buffer layer (Curatola II, first formed bulk (120)) suprajacent the substrate (Curatola II, (100)) with an intervening layer (Curatola II, (110); Fig. 4A-4C, Paragraph [0021]) formed between the first buffer layer and the substrate.
Claims 1, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable by Curatola II, in view of Okada et al. (U.S. Pub. 2013/0234156), hereinafter Okada, and Makiyama.
Regarding Claim 1, Curatola II teaches a method (Fig. 4A-4C, Paragraph [0030]) of forming a semiconductor device to reduce or counteract impurities at a regrowth interface, the method comprising:
forming a first semiconductor growth region (As in Fig. 4A), including:
forming a first buffer layer (‘bulk’ layer of (120) as first formed, including bottom surface, excluding where 2DEG will form, see also comparative example with 2DEG shown in Fig. 6A; Fig. 4A, Paragraph [0030]) of a first compound semiconductor material (e.g. GaN, Paragraph [0021]) on a substrate ((100); Fig. 4A, Paragraph [0021]);
forming a first channel layer (e.g. ‘top’ layer of (120) as first formed wherein the 2DEG forms, see also comparative example Fig. 6A) with the first buffer layer (bulk (120));
forming a first barrier layer ((240), subsequentially etched for regrowth and relabeled (140); Figs. 4A-4C, Paragraph [0033]) with the first channel layer (top (120) as first formed) thereby forming a first heterostructure, the first heterostructure configured to form a first two-dimensional electron gas (2DEG) channel (shown as the bottom dashed and dotted line below (220)/(140), Paragraphs [0030] and [0031]; Figs. 4A-4C, See also comparative exampled Fig. 6A); and
forming a second semiconductor growth region (As in Fig. 4B) at the regrowth interface, including:
forming a second heterostructure with the first semiconductor growth region, the second heterostructure configured to form a second 2DEG channel (shown as the top dashed and dotted line below (130), Paragraph [0030]; Figs. 4B-4C) and comprising a second channel layer (e.g. ‘top’ layer of regrowth portion of (120) wherein the second 2DEG forms); and
forming first and second spaced apart contact ((150) and (160); Fig. 4C, Paragraph [0030]) materials coupled to the second channel layer (top of regrowth (120)).
Curatola II’s method does not explicitly disclose:
-reducing or counteracting impurities at the regrowth interface;
Okada teaches a method of forming a multi-layer GaN device ((10); Figs. 3-6, Paragraph [0075]) including a regrown layer of GaN ((27); Fig. 6, Paragraph [0062]), comprising:
-reducing or counteracting impurities at the regrowth interface (Specifically by performing a hydrogen bake treatment, ‘thermal cleaning before the formation of the regrown layer’ Paragraph [0080] via hydrogen baking Paragraphs [0076] and [0077], See Figs. 5B and 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Okada into the method of Curatola II such that it includes a process of reducing or counteracting impurities at the regrowth interface. This would be due to the fact that doing so would restore dangling bonds and pacify impurities (Okada, Paragraph [0079]). See also instant Specification which recognizes this technique reduces impurities, Lines 1-11, Pg. 10; Figs. 5-7.
Neither Curatola II nor Okada explicitly teach:
- forming first and second isolation implant regions on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor device;
Makiyama teaches a method of manufacturing a semiconductor assembly (‘HEMT’; Figs. 1A-3C, Paragraph [0035]), comprising:
-forming first and second isolation implant regions (left and right (3); Fig. 3C, Paragraph [0046]) disposed on opposing lateral sides of the first barrier layer (e.g. (2e) of (2); Figs. 1A and 3C, Paragraph [0038])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Makiyama into the method of Curatola II as modified by Okada such that it comprises forming first and second isolation implant regions disposed on opposing lateral sides of the first barrier layer, the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly. This would be due to the fact that doing so would produce the predictable result of reducing leakage current between adjacent HEMTs / electrically isolating the HEMTS.
The limitation “the first and second isolation implant regions isolating the first 2DEG channel from interacting with the second 2DEG channel through sides of the semiconductor assembly” is necessarily fulfilled by the incorporation of the teachings of Makiyama as the isolation implant regions cover the full sides of the semiconductor stack. Please see also MPEP 2114 (I) regarding functional limitations.
For the following claim rejections, all references are directed towards Curatola II unless otherwise specified. For example, (120) refers to (Curtola II, (120)), while (Makiyama, (2)) refers to element (2) of Makiyama.
Regarding Claim 9, Curatola II as modified by Okada and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 1, wherein:
wherein reducing or counteracting impurities at the regrowth interface comprises:
performing a hydrogen bake treatment before forming the second semiconductor growth region (Curatola, as in Fig. 4B) to reduce the impurities at the regrowth interface (Okada, Paragraphs [0076], [0077], and [0080], Figs. 5B and 6).
Regarding Claim 10, Curatola II as modified by Okada and Makiyama teaches a method ((100); Fig. 1, Paragraph [0018]) of Claim 1, wherein:
forming the first buffer layer (Curatola II, first formed bulk (120)) of the first compound semiconductor material on the substrate (Curatola II, (100)) includes:
-forming the first buffer layer (Curatola II, first formed bulk (120)) suprajacent the substrate (Curatola II, (100)) with an intervening layer (Curatola II, (110); Fig. 4A-4C, Paragraph [0021]) formed between the first buffer layer and the substrate.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/DMITRI MIHALIOV/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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