DETAILED ACTION
This Office Action is in response to RCE filed December 11, 2025.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
On line 25, “a top surface” should be replaced with “the top surface”, because “a top surface of the first semiconductor layer” has already been recited on lines 14-15.
On lines 26-27, the limitation “a first position of the bottom surface of the first electrode at the first end position” should be amended, because (a) Applicants already claim “a first end position of the first electrode” on line 15, and (b) therefore, it appears that “a first position of the bottom surface of the first electrode at” in the limitation “a first position of the bottom surface of the first electrode at the first end position” is not necessary since it renders the limitation cited above rather awkward.
On line 28, along the same logic, the limitation “a second position of the bottom surface of the first electrode at” in the limitation “a second position of the bottom surface of the first electrode at the second end position” is not necessary since it renders the limitation cited above rather awkward.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 5, 22, 23 and 27 are rejected under 35 U.S.C. 101, because (a) the invention recited in claim 1 is directed to a drawing or an illustration shown in Fig. 10 of current application rather than being directed to an actual variable capacitance element structure, and thus is directed to an abstract idea that cannot be realized by one of ordinary skill in the art, (b) as discussed below under the Enablement requirement rejection, the limitation “a distance between a plane parallel to a top surface of the first semiconductor layer and a straight line connecting a first position of the bottom surface of the first electrode at the first end position and a second position of the bottom surface of the first electrode at the second end position monotonously decreases in a first direction from the second terminal toward the first electrode (emphasis added)” recited on lines 25-29 of the amended claim 1 requires that the top surface of the first semiconductor layer 103 shown in Fig. 10 of current application should be perfectly smooth with zero surface roughness and no surface corrugation contrary to what one of ordinary skill in the art would already know since any atomic corrugation of the top surface of the first semiconductor layer 103 would reduce the claimed distance at the peaks of the top surface of the first semiconductor layer 103, hindering the realization of the claimed monotonously decreasing distance, (c) however, this requirement is not met by Applicants’ original disclosure since a perfectly smooth top surface of the first semiconductor layer with zero surface roughness and no surface corrugation exists only in the schematic illustration shown in Fig. 10 of current application rather than in any actual device structure. Claims 2, 5, 22, 23 and 27 depend on claim 1, and therefore, claims 2, 5, 22, 23 and 27 also fail to comply with the 35 USC 101 requirement.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 5, 22, 23 and 27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention. Regarding claim 1, Applicants did not originally disclose that “a distance between a plane parallel to a top surface of the first semiconductor layer and a straight line connecting a first position of the bottom surface of the first electrode at the first end position and a second position of the bottom surface of the first electrode at the second end position monotonously decreases in a first direction from the second terminal toward the first electrode (emphasis added)” recited on lines 25-29 of the amended claim 1, because (a) the limitation “a plane parallel to a top surface of the first semiconductor layer” refers to the plane corresponding to the flat horizontal line shown below,
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(b) however, even though the topmost line of the first semiconductor layer 103 shown in Fig. 10 of current application appears to be a straight line, Applicants did not originally disclose that the topmost line of the first semiconductor layer 103 corresponds to any “plane” sine (i) Applicants did not originally disclose that all the drawings are exactly to the scale, (ii) Applicants did not originally disclose any plane associated with the first semiconductor layer 103 in Fig. 10 of current application, and (iii) Applicants did not originally disclose any growth conditions of the first semiconductor layer 103 shown in Fig. 10 of current application, and (c) rather, as shown in Fig. 1 of Narang et al. (“Improvement in surface morphology and 2DEG properties of AlGaN/ GaN HEMT,” Journal of Alloys and Compounds 815 (2020) 152283), an epitaxially grown semiconductor layer always has a certain degree of corrugation and surface roughness. Claims 2, 5, 22, 23 and 27 depend on claim 1, and therefore, claims 2, 5, 22, 23 and 27 also fail to comply with the written description requirement.
Claims 1, 2, 5, 22, 23 and 27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Regarding claim 1, if the claimed variable capacitance element is directed to a real structure of a variable capacitance element rather than a design or a schematic illustration of a variable capacitance element shown in Fig. 10 of current application, the claimed invention fails to comply with the Enablement requirement for the following reasons:
(A) Applicants claim that “a distance between a plane parallel to a top surface of the first semiconductor layer and a straight line connecting a first position of the bottom surface of the first electrode at the first end position and a second position of the bottom surface of the first electrode at the second end position monotonously decreases in a first direction from the second terminal toward the first electrode (emphasis added)” recited on lines 25-29 of the amended claim 1, which is shown by the distance between the first electrode 107 and the first semiconductor layer 103 in Fig. 10 of current application, which is directed to Applicants’ elected species;
(B) The claimed monotonously decreasing distance is predicated on an assumption that the top surface of the first semiconductor layer 103 is a perfectly and atomically flat surface with zero surface roughness and without any surface corrugation such that “a plane parallel to a top surface of the first semiconductor layer” recited on line 25 can be unambiguously defined;
(C) However, there are one major issue with regard to these assumptions: one of ordinary skill in the art cannot obtain an atomically smooth surface with zero roughness and without any surface corrugation as evidenced by Fig. 1 of Narang et al. (“Improvement in surface morphology and 2DEG properties of AlGaN/ GaN HEMT,” Journal of Alloys and Compounds 815 (2020) 152283), where the top surface of a topmost GaN layer of a HEMT device structure is shown to be corrugated with a surface roughness of several nanometers; in this case, when the actual surface of the claimed first semiconductor layer resembles the surface shown in Fig. 1 of Narang et al., even when the bottom surface of the claimed first electrode is a smooth curved surface as illustrated in Fig. 10 of current application, the claimed distance between the claimed plane parallel to the top surface of the first semiconductor layer and the claimed straight line would not “monotonously” decrease as Applicants claim in the amended claim 1, but rather would decrease, increase and then decrease multiple times tracking the peaks and valleys of the top surface of the first semiconductor layer, because the claimed distance would depend on the top surface roughness of the claimed first semiconductor layer, which Applicants did not originally disclose on how to control;
(D) Therefore, one of ordinary skill in the art already understands that, while one of ordinary skill in the art may design a variable capacitance element structure having a perfectly smooth top surface of the first semiconductor layer 103 having zero surface roughness and no surface corrugation such that “a distance between a plane parallel to a top surface of the first semiconductor layer and a straight line connecting a first position of the bottom surface of the first electrode at the first end position and a second position of the bottom surface of the first electrode at the second end position monotonously decreases in a first direction from the second terminal toward the first electrode (emphasis added)” recited on lines 25-29 of the amended claim 1, the top surface of the first semiconductor layer 103 inherently has a non-zero surface roughness as shown in the prior art reference of Narang et al. as discussed above, which would not allow one of ordinary skill in the art to achieve the limitation “a distance between a plane parallel to a top surface of the first semiconductor layer and a straight line connecting a first position of the bottom surface of the first electrode at the first end position and a second position of the bottom surface of the first electrode at the second end position monotonously decreases in a first direction from the second terminal toward the first electrode (emphasis added)” recited on lines 25-29 of the amended claim 1;
(E) Deposition of the first semiconductor layer 103 shown in Fig. 10 of current application has been commonly carried out by one of ordinary skill in the art for the past several decades, and thus depositing the first semiconductor layer 103 is highly predictable, but depositing the claimed first semiconductor layer and the first electrode to achieve the limitation “a distance between a plane parallel to a top surface of the first semiconductor layer and a straight line connecting a first position of the bottom surface of the first electrode at the first end position and a second position of the bottom surface of the first electrode at the second end position monotonously decreases in a first direction from the second terminal toward the first electrode (emphasis added)” recited on lines 25-29 of the amended claim 1 is not predictable, and is not possible since the achievement of the limitation cited above requires atomically smooth surfaces for the first semiconductor layer;
(F) Applicants did not originally disclose any specific deposition conditions of the claimed first semiconductor layer 103, and especially Applicants did not originally disclose how to obtain perfectly smooth surface for the claimed first semiconductor layer;
(G) Applicants did not originally disclose any working example where the claimed first semiconductor layer 103 and the first electrode 107 have the claimed distance that monotonously decreases as claimed except for the schematic illustrations; and
(H) As disclosed by Narang et al., the top surface of the first semiconductor layer would be corrugated having a non-zero surface roughness, rendering the claimed distance between the claimed straight line and the top surface of the fist semiconductor non-monotonously decreasing or alternating between increases and decreases, and Applicants did not originally disclose on how to enable one of ordinary skill in the art to realize the claimed monotonically decreasing distance.
Claims 2, 5, 22, 23 and 27 depend on claim 1, and therefore, claims 2, 5, 22, 23 and 27 also fail to comply with the Enablement requirement.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al., “Mechanism of Ti/Al/Ti/WAu-free ohmic contacts to AlGaN/GaN heterostructures via pre-ohmic recess etching and low temperature annealing,” APPLIED PHYSICS LETTERS 107 (2015) 262109
Wang et al., “Comparison of SiO2-based double passivation scheme by e-beam evaporation and PECVD for surface passivation and gate oxide in AlGaN/GaN HEMTs,” Microelectronic Engineering 109 (2013) pp. 24-27
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 May 12, 2026
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