DETAILED ACTION
This Office Action is in response to Application filed January 25, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants' election with traverse of Species I drawn to the display substrate recited in claims 1-16, Subspecies I drawn to the embodiment shown in Fig. 2 of current application, Sub-subspecies C drawn to the embodiment shown in Fig. 9(a) of current application, and Sub-sub-subspecies c drawn to the embodiment shown in Fig. 12(a) of current application in the reply filed on June 5, 2026 is acknowledged. The traversal is on the grounds of First and Second reasons that “Liu fails to disclose or suggest distinguishing technical features of claim 1” explained on pages 4-6 of the REMARKS/ARGUMENTS filed June 5, 2026. This is not found persuasive because as discussed below, Liu et al. disclose the all the claim limitations, especially when numerous limitations of claim 1 are indefinite as discussed below under 35 USC 112(b) rejections. The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim 1 is objected to because of the following informalities: on line 2, “the pixel circuits” should be replaced with “the plurality of pixel circuits”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear what “a compensation transistor” recited on lines 2-3 refers to, because (a) Applicants refer to the element T2 in Fig. 4 of current application as a compensation transistor, (b) however, as can be seen clearly in Fig. 4 of current application, the circled area corresponding to the alleged compensation transistor T2 in Fig. 4 of current application comprises only two orthogonal branches of the Gate, and a portion of the semiconductor layer PO without any source-drain conductive layer SD, and (c) therefore, the alleged compensation transistor T2 is not exactly a transistor, and in this case, it is not clear whether the claimed compensation transistor is an actual transistor that performs a certain function, or a structure comprising only two branches of a gate and a portion of a semiconductor layer as shown in Fig. 4 of current application.
(2) Also regarding claim 1, it is not clear what the limitation “the first pixel circuit is disposed at least partially directly opposite to the first light-emitting device (emphases added)” recited on lines 8-9 suggests, because (a) for Applicants to claim that the first pixel circuit is disposed “directly opposite” to the first light-emitting device, Applicants first need to claim which element or feature is interposed between the first pixel circuit and the first light-emitting device such that the first pixel circuit is disposed at least partially “directly opposite” to the first light-emitting device, (b) also, it is not clear whether the limitation cited above suggests that the first pixel circuit and the first light-emitting device are disposed at exactly the same level with each other since otherwise the first pixel circuit and the first light-emitting device would not be (at least partially) “directly opposite” to each other, (c) however, in a display device, it is a common practice that a pixel circuit including a transistor and a light-emitting device are formed at different levels, and therefore, it is not clear what the limitation cited above refers to, and (d) in addition, it is not clear what the phrase “at least partially” implies since the phrase “at least partially” can imply “entirely”, in which case, it is not clear whether Applicants claim that the height or facing area of the first pixel circuit and the height or facing area of the first light-emitting device are exactly the same when the first pixel circuit is disposed entirely directly opposite to the first light-emitting device.
(3) Further regarding claim 1, it is not clear what “the first pixel circuit” and “the first light-emitting device” recited in the limitation “the first pixel circuit is disposed at least partially directly opposite to the first light-emitting device (emphases added)” recited on lines 8-9 refer to, because (a) unlike the simplified diagrams of pixel circuits 10 and the light-emitting devices 20 shown in Fig. 2 of current application, each of the first pixel circuit and the first light-emitting device has an actual, complex device structure, (b) for example, the first light-emitting device should comprise at least a cathode, a light-emitting layer and an anode, and then the cathode and the anode should be connected to the outside world or to other circuit elements by electrical wirings or connectors, in which case, it is not clear whether those electrical wirings or connectors are parts of the first pixel circuit or the first light-emitting device, (c) however, Applicants do not claim any specific structures of the first pixel circuit and the first light-emitting device even though Applicants claim that the first pixel circuit and the first light-emitting device are disposed at least partially directly opposite to each other, (d) if, for example, both the first pixel circuit and the first light-emitting device are electrically connected by vertical wirings or connectors, and when those vertical wirings or connectors are parts of the claimed first pixel circuit or the first light-emitting device, the first pixel circuit and the first light-emitting device would not be at least partially directly opposite to each other since the first pixel circuit and the first light-emitting device would overlap with each other in a cross sectional view, (e) furthermore, if the claimed first pixel circuit includes a power supply embedded on the display substrate or an outside power supply, then the first pixel circuit would be a macroscopic structure, while the first light-emitting device may be a microscopic structure, in which case, one cannot say that the first pixel circuit, which is a macroscopic structure including the power supply, is disposed at least partially directly opposite to the first light-emitting device, which is a microscopic structure, and (f) in other words, without Applicants’ specifically claiming the exact structures of the claimed first pixel circuit and the first light-emitting device, one would not be able to determine unambiguously whether the first pixel circuit and the first light-emitting device are disposed at least partially directly opposite to each other.
(4) Still further regarding claim 1, it is not clear what the limitation “a plane where the display substrate is located” recited on line 11 suggests, because (a) the claimed display substrate should be a three dimensional structure, which cannot exactly be located in “a plane”, which is an abstract, two dimensional mathematical concept, (b) therefore, while arguendo one horizontal level of the claimed display substrate may be located in “a plane”, the display substrate itself cannot be located in “a plane”, (c) since the claimed display substrate cannot be completely contained in a single “plane”, the “plane” can be arbitrarily selected, (d) therefore, while a plane parallel to the device structure shown in Fig. 2 of current application may be selected, a plane perpendicular to the device structure shown in Fig. 2 of current application can also be selected, and (e) however, Applicants do not simply claim “a plane where the display substrate is located”, but rather claim that the orthographic projections of the second pixel circuit and the second light-emitting device have no overlap as recited on lines 10-13, which would strongly depend on what “a plane” refers to, which Applicants do not specifically claim.
(5) Still further regarding claim 1, it is not clear how “a second pixel circuit is coupled to a second light-emitting device” as recited on line 10, and then the orthographic projections of the second pixel circuit and the second light-emitting device on the plane where the display substrate is located can have no overlap as recited on lines 10-13, because (a) for the second pixel circuit 12 to be coupled to the second light-emitting device 22 in Fig. 4 of current application, the second pixel circuit 12 and the second light-emitting device 22 should be electrically connected as illustrated below,
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(b) however, Applicants did not originally disclose and do not specifically claim how the second pixel circuit 12 and the second light-emitting device 22 are electrically connected, which is also discussed below, and (c) therefore, it appears that the limitation recited on lines 10-13 is directed to the diagrams shown in Fig. 2 of current application rather than an actual display substrate, rendering claim 1 further indefinite.
(6) Still further regarding claim 1, it is not clear what the second pixel circuit and the second light-emitting device each refers to, because (a) as discussed above, while Applicants may have provided simplified diagrams of the second pixel circuit 12 and the second light-emitting device 22 in Fig. 2 of current application, actual second pixel circuit and the second light-emitting device should also include wirings or connectors electrically connected the second pixel circuit 12 and the second light-emitting device 22 shown in Fig. 2 of current application, (b) when those not-shown wirings or connectors are included as parts of the claimed second pixel circuit or second light-emitting device, it is not clear whether the orthographic projections of the second pixel circuit and the second light-emitting device would overlap or would not overlap, which depends on the exact and complete structures of the second pixel circuit and the second light-emitting device, and (c) therefore, without Applicants’ specifically claiming what the second pixel circuit and the second light-emitting device are constituted of, one cannot unambiguously determine whether there would be no overlap between the orthographic projections of the second pixel circuit and the second light-emitting device.
(7) Still further regarding claim 1, it is not clear what the limitation “a width-to-length ratio of a channel” recited on lines 15 and 16 each refers to, because (a) Applicants do not claim a channel layer, but rather claim “a channel”, (b) formation of “a channel”, unlike a channel layer, depends on the operating conditions of the driving transistors of the first and second pixel circuit, and (c) therefore, the limitation recited on lines 15-16 comparing the width-to-length ratios of the channel of the driving transistors in the first and second pixel circuit depends on the operating conditions, and thus may or may not be satisfied even for a single display substrate depending on the operating conditions, rendering claim 1 further indefinite.
(8) Still further regarding claim 1, it is not clear what the “width” and “length” of the channel of the driving transistors in the first and second pixel circuit refer to, because (a) it does not appear that the “width” is an actual width of the channel, but rather an average value of a plurality of widths as Applicants disclosed in paragraph [0175] of current application in describing Fig. 8a of current application, (b) however, Applicants do not claim “an average width-to-length ratio” on lines 15-16, and therefore, it is not clear whether the claimed width-to-length ratio includes a single width or an average width of the channel, (c) in addition, even though Applicants originally disclosed a sum of lengths in paragraph [0185] of current application in view of Fig. 8b of current application, the example shown in Fig. 8b of current application is only one way to define a channel length with the other ways being defining a channel length along the centerlines or the bottommost lines of the semiconductor layer PO in Fig. 8b of current application, which are different from the channel length shown in Fig. 8b of current application, and (d) furthermore, an actual channel of a driving transistor of a pixel circuit should not be the transistor T3 shown in Fig. 4 of current application, but rather the rectangular area illustrated below since only the rectangular area illustrated below are disposed between the source-drain conductive layer SD, and the remaining area of the semiconductor layer PO does not function as a channel, which renders claim 1 further indefinite since it is not clear what the “channel” refers to and what the channel length refers to.
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(9) Still further regarding claim 1, it is not clear what the limitation “a channel capacitance” recited on lines 17-18 refers to, because (a) for Applicants to claim a channel capacitance, Applicants first need to claim how the channel capacitance is defined, (b) in addition, it is not clear whether the channel is an insulator since a capacitance of a structural element is associated with a capacitor comprising an insulator sandwiched by two electrodes, (c) however, it does not appear that the channel is an insulator, (d) also, a capacitance is defined as follows,
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and therefore, a channel capacitance in a vertical direction of the display substrate would be differ from a channel capacitance in a lateral direction of the display substrate since at least the distance between the two plates are different when the channel capacitance is measured in the vertical direction and in the lateral direction, and (e) therefore, the comparison of the channel capacitance of the compensation transistors in the first and second pixel circuit recited on lines 17-18 cannot be determined unambiguously without Applicants’ specifically claiming any capacitor structure associated with the claimed channel capacitance.
(10) Still further regarding claim 1, it is not clear what “a channel capacitance” recited on lines 17-18 refers to, because (a) Applicants do not claim a channel layer capacitance, but rather claim a channel capacitance, and (b) as discussed above, a size and a location of a channel would depend on operating conditions of a transistor, which Applicants do not specifically claim, rendering claim 1 further indefinite.
(11) Still further regarding claim 1, it is not clear how the channel capacitance recited on lines 17-18 can be measured unambiguously, because (a) the portion of the semiconductor layer PO in the alleged compensation transistor T2 in Fig. 4 of current application is merely a small part of the semiconductor layer PO, (b) therefore, however the channel capacitance is defined, the channel capacitance would be different depending on where two probes for the measurement of the capacitance of the channel are placed on the contiguous semiconductor layer PO, and (c) the remaining portion of the semiconductor layer PO would also influence the measurement of the capacitance of the channel capacitance of a compensation transistor, rendering “a channel capacitance” inconsistent and unclear.
Claims 2-16 depend on claim 1, and therefore, claims 2-16 are also indefinite.
(12) Regarding claims 2, 4 and 8, claims 2, 4 and 8 are indefinite for the same reasons stated above with regard to “a channel width”; in other words, it is not clear whether “a channel width” recited on lines 1 and 2 of claims 2, 4 and 8 are an average channel width or a single channel width along one direction. Claim 3 depends on claim 2, and claims 9 and 10 depend on claim 8, and therefore, claims 3, 9 and 10 are also indefinite.
(13) Regarding claims 5, 7 and 11, claims 5, 7 and 11 are indefinite for the same reasons stated above with regard to “a channel length”; in other words, the “channel” length would vary depending on the operating conditions of the claimed transistors. Claim 6 depends on claim 5, and claims 12 and 13 depend on claim 11, and therefore, claims 6, 12 and 13 also indefinite.
(14) Regarding claim 15, claim 15 is indefinite for the same reasons stated above with regard to “a width-to-length ratio of channel” and “channel capacitance” recited in claim 1, because claim 15 recites “width-to-length rations of channels” on lines 1-2 and “channel capacitances” on line 4.
(15) Also regarding claim 15, it is not clear what the phrase “negatively correlated” recited on lines 2 and 5 suggests, because it is not clear whether there are a plurality of values of width-to-length ratios of channels, a plurality of values of lengths of the leads and a plurality of values of channel capacitances since, if there is only one value for the width-to-length ratios of channels, only one value of the length of the leads, and only one value of channel capacitances, the phrase “negatively correlated” would be ambiguous; in other words, one cannot tell whether one value of width-to-length ratios of channels of, for example, 10 and one value of lengths of the leads of, for example, 1 micron are negatively correlated with each other.
(16) Further regarding claim 15, it is not clear what the “lengths of the leads” recited on lines 2-3 refer to, because (a) as discussed above with regard to claim 1, Applicants do not specifically claim what the second pixel circuit and the second light-emitting device recited in claims 1 and 14 are constituted of, and (b) therefore, without fully and exactly understanding what the structural elements of the second pixel circuit and the second light-emitting device are, one cannot unambiguously determine what “the leads” are, and therefore, what “the lengths of the leads” are.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15, as best understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (WO 2021/016946)
Regarding claim 1, Liu et al. disclose a display substrate (Figs. 3-6), comprising a plurality of pixel circuits (circuits for R and B in Fig. 5 or Fig. 6) and a plurality of light-emitting devices (Fig. 6C); and the pixel circuits each including a driving transistor (one of transistors in Fig. 3) and a compensation transistor (another of transistors in Fig. 3) coupled to the driving transistor, because (a) it does not appear that the verb “coupled” necessarily suggests “electrically connected” since the driving transistor T3 and the compensation transistor T2 in Fig. 4 of current application are not electrically connected to each other, and (b) therefore, the plurality of transistors shown in Fig. 3 of Liu et al. are coupled to each other; wherein the plurality of pixel circuits include a plurality of first pixel circuits (pixel circuits corresponding to R or B in Fig. 5 or Fig. 6) and a plurality of second pixel circuits (pixel circuits corresponding to B or R in Fig. 5 or Fig. 6); the plurality of light-emitting devices include a plurality of first light-emitting devices (light-emitting devices shown in Fig. 6C coupled to R or B) and a plurality of second light-emitting devices (light-emitting devices shown in Fig. 6C coupled to B or R); a first pixel circuit is coupled to a first light-emitting device, which is inherent to form a functioning display device, and the first pixel circuit is disposed at least partially directly opposite to the first light-emitting device, because this limitation is indefinite as discussed above under 35 USC 112(b) rejections; a second pixel circuit is coupled to a second light-emitting device, which is inherent to form a functioning display device, and an orthographic projection of the second pixel circuit on a plane where the display substrate is located and an orthographic projection of the second light-emitting device on the plane where the display substrate is located have no overlap, because (a) this limitation is indefinite as discussed above under 35 USC 12(b) rejections, and (b) the pixels R and B are separated as shown in Figs. 5 and 6 of Liu et al.; wherein the first pixel circuit and the second pixel circuit satisfy at least one of: a width-to-length ratio of a channel of a driving transistor in the first pixel circuit is greater than a width-to-length ratio of channel of driving transistor in the second pixel circuit; and a channel capacitance of compensation transistor in the first pixel circuit is larger than a channel capacitance of a compensation transistor in the second pixel circuit, because (a) these two limitations are indefinite as discussed above under 35 USC 112(b) rejections, and (b) as discussed above, a channel length would depend on operating conditions, and therefore, the relative width-to-length ratio of the channels of the driving transistors in the first and second pixel circuit would meet the first relationship recited on lines 15-16 of claim 1 under certain operating conditions.
Regarding claims 2-15, Liu et al. disclose that a channel width of the driving transistor in the first pixel circuit is larger than a channel width of the driving transistor in the second pixel circuit, because this limitation is indefinite as discussed above under 35 USC 112(b) rejections (claim 2), wherein a difference between the channel width of the driving transistor in the first pixel circuit and the channel width of the driving transistor in the second pixel circuit is less than or equal to 0.6 µm, because the channel widths can be arbitrarily defined to meet the claim limitation of claim 3 (claim 3), a ratio of a channel width of the driving transistor in the first pixel circuit to a channel width of the driving transistor in the second pixel circuit is greater than 1 and less than or equal to 1.21, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the channel widths can be arbitrarily defined to meet the claim limitation of claim 4 (claim 4), a channel length of the driving transistor in the first pixel circuit is smaller than a channel length of the driving transistor in the second pixel circuit, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the operating conditions of the two driving transistors can be arbitrarily selected to meet the claim limitation of claim 5 (claim 5), wherein a difference between the channel length of the driving transistor in the first pixel circuit and the channel length of the driving transistor in the second pixel circuit is less than or equal to 1.4 µm, because the channel lengths can be selected by controlling the operating conditions of the two transistors to meet the claim limitation of claim 6 (claim 6), a ratio of a channel length of the driving transistor in the first pixel circuit to a channel length of the driving transistor in the second pixel circuit is less than 1 and greater than or equal to 0.94, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the operating conditions of the two driving transistors can be arbitrarily selected to meet the claim limitation of claim 7 (claim 7), a channel width of the compensation transistor in the first pixel circuit is larger than a channel width of the compensation transistor in the second pixel circuit, because this limitation is indefinite as discussed above under 35 USC 112(b) rejections (claim 8), wherein a difference between the channel width of the compensation transistor in the first pixel circuit and the channel width of the compensation transistor in the second pixel circuit is less than or equal to 0.3 µm, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the channel widths can be arbitrarily defined to meet the claim limitation of claim 9 (claim 9), and a ratio of the channel width of the compensation transistor in the first pixel circuit to the channel width of the compensation transistor in the second pixel circuit is greater than 1 and less than or equal to 1.14, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the channel widths can be arbitrarily defined to meet the claim limitation of claim 10 (claim 10), a channel length of the compensation transistor in the first pixel circuit is larger than a channel length of the compensation transistor in the second pixel circuit, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the operating conditions of the two compensation transistors can be arbitrarily selected to meet the claim limitation of claim 11 (claim 11), wherein a difference between the channel length of the compensation transistor in the first pixel circuit and the channel length of the compensation transistor in the second pixel circuit is less than or equal to 0.8 µm, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the operating conditions of the two compensation transistors can be arbitrarily selected to meet the claim limitation of claim 12 (claim 12), and a ratio of the channel length of the compensation transistor in the first pixel circuit to the channel length of the compensation transistor in the second pixel circuit is greater than 1 and less than or equal to 1.15, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the operating conditions of the two compensation transistors can be arbitrarily selected to meet the claim limitation of claim 13 (claim 13), further comprising a plurality of leads (wirings shown in Figs. 3-6); wherein the second pixel circuit is coupled to the second light-emitting device by a lead, which is inherent to form a functioning display device (claim 14), wherein width-to-length ratios of channels of driving transistors in the second pixel circuits are negatively correlated to lengths of the leads respectively connected to the second pixel circuits; and/or channel capacitances of compensation transistors in the second pixel circuits are negatively correlated to the lengths of the leads respectively connected to the second pixel circuits, because these limitations are indefinite as discussed above under 35 USC 112(b) rejections (claim 15).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (US 2022/0254855)
Zhang et al. (US 12,550,429)
Xing (US 11,811,004)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 June 17, 2026
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