DETAILED ACTION
This action is responsive to the application No. 18/291,983 filed on January 25, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 reading on Figs. 4, 24, and 29 in the reply filed on 05/14/2026 is acknowledged. The applicants indicated that claims 1, 7-13, 16, and 17 read on the elected invention. Accordingly, claims 2-6, 14, 15, and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 12, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho (US 2021/0249498).
Regarding Claim 1, Chou (see, e.g., Figs. 1-12, and Annotated Figs. 4, 6G), teaches a display panel 200 (see, e.g., par. 0175), comprising:
a driving backplane BP comprising a substrate 100 and a circuit layer CL, a wiring layer WL and a first planarization layer 119 which are stacked in sequence along a direction D3 away from the substrate 100 (see, e.g., pars. 0051, 0070, 0081, 0082, 0153);
wherein:
the circuit layer CL comprises a plurality of pixel circuits distributed in an array (see, e.g., Figs. 1-2, pars. 0053, 0058);
the wiring layer WL comprises data lines 181 and power lines 183 distributed along a row direction D1, and one of the data lines 181 and one of the power lines 183 are connected to a column of the pixel circuits (see, e.g., Fig. 3, par. 0081);
the power lines 183 have a width larger than that of the data lines 181 (see, e.g., Figs. 3, 6G);
the power lines 183 are provided with a plurality of through-holes TH distributed in a column direction D2, the through-holes TH are provided with interconnection portions 185 which are arranged in a same layer as the power lines 183 and are spaced from the power lines 183, and one of the interconnection portions 185 is connected to one of the pixel circuits (see, e.g., Fig. 6G, Annotated Fig. 6G, pars. 0150, 0153);
a plurality of light-emitting devices OLED distributed in an array on a side of the first planarization layer 119 away from the substrate 100 and connected to the pixel circuits, wherein each of the light-emitting devices OLED comprises a first electrode 310, a light-emitting layer 320 and a second electrode 330 which are stacked in sequence along the direction D3 away from the substrate 100, the light-emitting devices OLED comprises at least two kinds of light-emitting devices OLED which emit light of different colors, and at least part of the light-emitting devices OLED overlap with an area of the power lines 183 where no through-hole TH is provided (see, e.g., Fig. 4, pars. 0018, 0053, 0092, 0155-0158); and
an anti-reflection layer 400 arranged on a side of the light-emitting devices OLED away from the substrate 100, and comprising a plurality of filter portions distributed in an array, wherein one of the filter portions overlaps with one of the light-emitting devices OLED, and a color of one of the filter portions is the same as a color of light emitted by a light-emitting device OLED which overlaps with the one of the filter portions (see, e.g., Fig. 12, par. 0180).
Regarding Claim 12, Chou teaches all aspects of claim 1. Chou (see, e.g., Figs. 1-12, and Annotated Figs. 4, 6G), teaches that:
each of the pixel circuits comprises a plurality of transistors T1-T7 (see, e.g., Fig. 2, par. 0058);
the circuit layer CL comprises a semiconductor layer AS1, a first gate insulating layer 112, a first gate layer G1, a second gate insulating layer 113, a second gate layer G2, a dielectric layer 114, a source-drain layer S4/D4, a passivation layer 116, and a second planarization layer 118 which are distributed along the direction D3 away from the substrate 100 (see, e.g., pars. 0087-0088, 0090, 0097);
the wiring layer WL is arranged on a side of the second planarization layer 118 away from the substrate 100; and
channels A1-A7 of the transistors T1-T7 are located in the semiconductor layer AS1.
Regarding Claim 16, Chou (see, e.g., Figs. 1-12, and Annotated Figs. 4, 6G), teaches a display device, comprising a display panel 200 (see, e.g., pars. 0049, 0175), wherein the display panel 200 comprises:
a driving backplane BP comprising a substrate 100 and a circuit layer CL, a wiring layer WL and a first planarization layer 119 which are stacked in sequence along a direction D3 away from the substrate 100 (see, e.g., pars. 0051, 0070, 0081, 0082, 0153);
wherein:
the circuit layer CL comprises a plurality of pixel circuits distributed in an array (see, e.g., Figs. 1-2, pars. 0053, 0058);
the wiring layer WL comprises data lines 181 and power lines 183 distributed along a row direction D1, and one of the data lines 181 and one of the power lines 183 are connected to a column of the pixel circuits (see, e.g., Fig. 3, par. 0081);
the power lines 183 have a width larger than that of the data lines 181 (see, e.g., Figs. 3, 6G);
the power lines 183 are provided with a plurality of through-holes TH distributed in a column direction D2, the through-holes TH are provided with interconnection portions 185 which are arranged in a same layer as the power lines 183 and are spaced from the power lines 183, and one of the interconnection portions 185 is connected to one of the pixel circuits (see, e.g., Fig. 6G, Annotated Fig. 6G, pars. 0150, 0153);
a plurality of light-emitting devices OLED distributed in an array on a side of the first planarization layer 119 away from the substrate 100 and connected to the pixel circuits, wherein each of the light-emitting devices OLED comprises a first electrode 310, a light-emitting layer 320 and a second electrode 330 which are stacked in sequence along the direction D3 away from the substrate 100, the light-emitting devices OLED comprises at least two kinds of light-emitting devices OLED which emit light of different colors, and at least part of the light-emitting devices OLED overlap with an area of the power lines 183 where no through-hole TH is provided (see, e.g., Fig. 4, pars. 0018, 0053, 0092, 0155-0158); and
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an anti-reflection layer 400 arranged on a side of the light-emitting devices OLED away from the substrate 100, and comprising a plurality of filter portions distributed in an array, wherein one of the filter portions overlaps with one of the light-emitting devices OLED, and a color of one of the filter portions is the same as a color of light emitted by a light-emitting device OLED which overlaps with the one of the filter portions (see, e.g., Fig. 12, par. 0180).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2021/0249498) in view of Kim (US 2023/0217749).
Regarding Claim 17, Cho teaches all aspects of claim 16. Cho is silent with respect to the claim limitation that the first electrode is made of a reflective material.
Kim (see, e.g., Fig. 6), in similar display devices to Cho, on the other hand, teaches that the first electrode 310R/310G/310B is made of a reflective material, to prevent the lower wiring configuration from being visible (see, e.g., par. 0059).
It would have been obvious to one of ordinary skill in the art at the time of filing to have in Cho’s device, the first electrode made of a reflective material, as taught by Kim, to prevent the lower wiring configuration from being visible.
Allowable Subject Matter
Claims 7-11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814
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