Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 01/25/2024. Currently, claims 1-26 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Negley (Pub. No. US 2005/0211999 A1).
Regarding claim 1, Negley discloses a method of manufacturing a nitride semiconductor device (Abstract; p-type GaN based semiconductor device), the method comprising: a magnesium layer formation step ([0015]) of forming a magnesium layer 13 ([0041]) that comprises magnesium as a major component on a surface of a nitride semiconductor substrate 11/16 ([0026], [0030]); and an annealing step of annealing the nitride semiconductor substrate on which the magnesium layer is formed ([0016]-[0017], [0033]).
Claims 16-20 and 22-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokogawa et al. (Pub. No. US 2013/0119398 A1).
Regarding claim 16, Yokogawa discloses a nitride semiconductor device comprising: a nitride semiconductor substrate 10-26 ([0074]) having a p-type region 26 ([0087]) exposed on at least a part of its surface (Fig. 3); an intermediate layer 32 arranged at least in a part of an upper surface of the p-type region and containing magnesium and nitrogen (claim 1, [0025], [0040]); and an electrode layer 34 arranged on at least a part of an upper surface of the intermediate layer ([0078]).
Regarding claim 17, Yokogawa inherently discloses the nitride semiconductor device according to claim 16, wherein the intermediate layer has an amorphous structure (In a GaN device, the magnesium-rich layer is substantially amorphous (lacking long-range crystal order) because the high magnesium concentration disrupts the long-range crystalline ordering of gallium nitride, preventing formation of a continuous crystalline lattice. Additionally, the amorphous nature of the magnesium-containing layer results from deposition conditions that limit atomic mobility and suppress crystal growth.).
Regarding claim 18, Yokogawa discloses the nitride semiconductor device according to claim 16, wherein the intermediate layer contains gallium, and a concentration of the gallium in the intermediate layer decreases as a distance from an interface between the p-type region and the intermediate layer increases (Fig. 12).
Regarding claim 19, Yokogawa discloses the nitride semiconductor device according to claim 16, wherein an impurity concentration of the p-type region is in a range of 1 x1016 to 1 x1020 cm-3 ([0097]).
Regarding claim 20, Yokogawa discloses the nitride semiconductor device according to claim 16, wherein a thickness of the intermediate layer is 1000 nm or less ([0022], [0023], [0090]).
Regarding claim 22, Yokogawa discloses the nitride semiconductor device according to claim 16, wherein the nitride semiconductor substrate is gallium nitride, and the intermediate layer is magnesium nitride (Abstract and [0074]).
Regarding claim 23, Yokogawa shows a nitride semiconductor substrate (Abstract, [0001]), wherein a magnesium concentration distribution in a direction perpendicular to a surface of the nitride semiconductor substrate has a maximum value (Figs. 3, 11) within a first region from the surface to a depth of 100 nanometers (Fig. 11: distances below 0.10 µm on the graph), and the maximum value is 1 x1020 cm-3 or more ([0123]-[0126] and Fig. 11: Mg concentration of up to 3 x1022 atoms/cm3 on the graph).
Regarding claim 24, Yokogawa discloses the nitride semiconductor substrate according to claim 23, wherein the magnesium concentration distribution varies in concentration by one or more orders of magnitude within a second region extending in a depth direction from the maximum value and having a width of 100 nanometers or less ([0123]-[0126] and Fig. 11).
Regarding claim 25, Yokogawa discloses the nitride semiconductor substrate according to claim 24, wherein the magnesium concentration distribution has a singularity point, at which a concentration gradient becomes sharply smaller, in the second region, a constant concentration region is present, in which a magnesium concentration is substantially constant in the depth direction from the singularity point, and a width of the constant concentration region in the depth direction is 50 nanometers or more ([0123]-[0126] and Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4-6, 8-11 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Negley in view of Shimizu (Pub. No. US 2021/0118984 A1).
Regarding claim 2, Negley discloses wherein in the magnesium layer formation step, the magnesium layer is formed on at least a part of a surface of a p-type region 11 ([0026]) of the nitride semiconductor substrate ([0026], [0030]) having the p-type region exposed on at least a part of its surface (Fig. 3 and [0056]; the areas that are only under the layer 14 are considered to be the exposed areas), in the annealing step, the nitride semiconductor substrate on which the magnesium layer is formed is annealed ([0016]-[0017], [0033]), and the method further comprises an electrode formation step of forming an electrode layer 22 ([0058]) on at least a part of an upper surface of the intermediate layer (Fig. 3).
Negley does not specifically state in the annealing step, the nitride semiconductor substrate on which the magnesium layer is formed is annealed in an atmosphere containing nitrogen to transform the magnesium layer into an intermediate layer containing magnesium and nitrogen.
However, in the same field of endeavor, Shimizu teaches a nitride semiconductor device, comprising: in the annealing step ([0062], [0065]), the nitride semiconductor substrate on which the magnesium layer is formed is annealed in an atmosphere containing nitrogen ([0091], [0092]) to transform the magnesium layer into an intermediate layer containing magnesium and nitrogen ([0046]) to improve the threshold voltage ([0069]).
Therefore, given the teachings of Shimizu, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Negley in view of Shimizu by employing the annealing in an atmosphere containing nitrogen.
Regarding claim 4, Negley in view of Shimizu teaches the method of manufacturing a nitride semiconductor device according to claim 2, wherein an impurity concentration of the p-type region is in a range of 1 x1016 to 1 x1020 cm-3 (Negley: [0004]).
Regarding claim 5, Negley in view of Shimizu teaches the method of manufacturing a nitride semiconductor device according to claim 2, wherein in the magnesium layer formation step, the magnesium layer is selectively formed in a specific region that is at least a part of the surface of the p-type region (Negley: [0004] and Fig. 3).
Regarding claim 6, Negley in view of Shimizu teaches the method of manufacturing a nitride semiconductor device according to claim 5, wherein the magnesium layer formation step comprises: a step of forming, a mask layer including an opening corresponding to the specific region, on a surface of the nitride semiconductor substrate; and a step of depositing the magnesium layer via the mask layer (Negley: [0056] and Fig. 3).
Regarding claim 8, Negley in view of Shimizu teaches the method of manufacturing a nitride semiconductor device according to claim 2, wherein the nitride semiconductor substrate is gallium nitride (Negley: Abstract).
Regarding claim 9, Negley in view of Shimizu intrinsically teaches the method of manufacturing a nitride semiconductor device according to claim 1, further comprising: a defect formation step of forming crystal defects in the nitride semiconductor substrate from a surface of nitride semiconductor substrate, wherein the magnesium layer is a solid layer (Negley: [0015], [0026]).
Regarding claim 10, Negley in view of Shimizu teaches the method of manufacturing a nitride semiconductor device according to claim 9, further comprising: a protective layer formation step of forming a protective layer on a surface of the magnesium layer, wherein in the annealing step, the nitride semiconductor substrate on which the protective layer is formed is heated (Negley: [0008]-[0011]).
Regarding claim 11, Negley in view of Shimizu teaches the method of manufacturing a nitride semiconductor device according to claim 10, further comprising: a pre-annealing step of heating the nitride semiconductor substrate at a lower temperature than in the annealing step, wherein the pre-annealing step is performed after the magnesium layer formation step and before the protective layer formation step. (Negley: [0006], [0009], [0033]).
Regarding claim 13, Negley in view of Shimizu characteristically teaches the method of manufacturing a nitride semiconductor device according to claim 1, further comprising: a defect formation step of forming crystal defects in the nitride semiconductor substrate from a surface of nitride semiconductor substrate, wherein the magnesium layer is a melt containing magnesium (Negley: [0015], [0026]).
Regarding claim 14, Negley in view of Shimizu intrinsically teaches the method of manufacturing a nitride semiconductor device according to claim 13, wherein the melt contains Zn, and a temperature of the melt is 450 ºC or higher (Negley: [0033], [0051] and Shimizu: [0062]).
Regarding claim 15, Negley in view of Shimizu intrinsically teaches the method of manufacturing a nitride semiconductor device according to claim 9, wherein the defect formation step comprises a step of implanting nitrogen ions from a surface of the nitride semiconductor substrate (Negley: [0015], [0026]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yokogawa.
Regarding claim 26, Yokogawa does not specifically disclose a planar density of loop defects in a cross-sectional view of a region where magnesium is added is 1x105 [pcs/cm2] or less ([0122]). However, it is known that Mg incorporation introduces strain and point defects. Excess vacancies can aggregate during growth or annealing. Vacancy clusters may evolve into dislocation loop, often observed by TEM. Increased loop density is usually correlated with poorer PL efficiency because carriers recombine non-radiatively at these defects. Therefore, in a GaN device with Mg layer, an increase in vacancy defect density generally promotes the formation of loop defects, and both tends to reduce photoluminescence efficiency, although the exact relationship depends on growth temperature, Mg concentration, and post-growth annealing conditions. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed density range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Allowable Subject Matter
Claims 3, 7, 12 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising: a step of decreasing a film thickness of the intermediate layer that is performed after the annealing step, wherein the electrode formation step forms the electrode layer on the upper surface of the intermediate layer after having decreased the film thickness.
With respect to claim 7, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein an n-type region is exposed on a part of a surface of the nitride semiconductor substrate, in the magnesium layer formation step, the magnesium layer is formed on at least a part of the surface of the p-type region but is not formed on a surface of the n-type region, and in the electrode layer formation step, the electrode layer is formed to traverse across the intermediate layer that is formed in the p-type region and the n-type region.
With respect to claim 12, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising: a step of removing an altered layer formed on the surface of the magnesium layer by the pre-annealing step, wherein the protective layer is formed on the surface of the magnesium layer from which the altered layer has been removed.
With respect to claim 21, the prior art of record alone or in combination do not teach or fairly suggest, further comprising: an n-type region exposed on a part of a surface of the nitride semiconductor substrate, wherein the electrode layer is formed to traverse across the n-type region and the p-type region, and the intermediate layer is arranged between the p-type region and the electrode layer but is not arranged between the n-type region and the electrode layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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June 11, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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