DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 13 August 2026 have been fully considered but they are not persuasive.
Applicant’s argument is that Noda does not disclose "a bias feedback network coupled between the input terminal of the output amplifier stage and the biasing leg," as recited by claim 1.
This is not persuasive because Noda discloses that the bias feedback network 3 is connected to the input of the output amplifier (M5 gate) via element M7 and the bias feedback network 3 is connected to the bias leg element M6 at node JA. Therefore, the bias feedback network 3 is connected between the input of the output amplifier and the biasing leg as required by claim 1. Additionally, the claims do not require that the bias feedback network is directly connected to the input of the output amplifier or that the bias feedback network layout is physically arranged between the output amplifier and the biasing leg.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9, 13-14, 17-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noda (US 8,471,548).
In regard to Claim 1:
Noda discloses, in Figure 2, an amplifier with bias stabilization, comprising:
an output amplifier stage (M5) comprising an input terminal (M5 gate);
a biasing leg (4) comprising a biasing node (J67) coupled to the input terminal of the output amplifier stage (J67 is coupled to M5 gate); and
a bias feedback network (3) coupled between the input terminal of the output amplifier stage (M5 gate) and the biasing leg (4).
In regard to Claim 2:
Noda discloses, in Figure 2, the amplifier according to claim 1, wherein the biasing leg (4) comprises a first biasing transistor (M7) and a second biasing transistor (M6).
In regard to Claim 3:
Noda discloses, in Figure 2, the amplifier according to claim 2, wherein:
the first biasing transistor (M7) comprises a collector coupled to a source voltage (VDD), an emitter coupled to the second biasing transistor (M7 and M6 connection), and a base coupled to an input of the amplifier (M7 gate connected to M5 gate via M6 body, I1, and M2); and
the second biasing transistor (M6) comprises a collector coupled to the first biasing transistor (M7), an emitter coupled to ground (M6 connected to ground), and a base coupled to a bias control signal from the bias feedback network (JB of 3 connected to M6 gate).
In regard to Claim 6:
Noda discloses, in Figure 2, The amplifier according to claim 1, wherein the bias feedback network comprises a difference amplifier (M1-M4), a bypass stage (M8), and a reference voltage generator (2).
In regard to Claim 7:
Noda discloses, in Figure 2, the amplifier according to claim 6, wherein:
a first input of the difference amplifier (M1-M4) is coupled to the input terminal of the output amplifier stage (Vout at JV1 connected to M2 gate);
a second input of the difference amplifier (M1-M4) is coupled to an output of the reference voltage generator (M1 gate connected to 2); and
the difference amplifier (M1-M4) generates a bias control signal (J47 and JB outputs) based on a difference between the first input and the second input of the difference amplifier (Column 3: lines 12-22 and 29-47).
In regard to Claim 8:
Noda discloses, in Figure 2, the amplifier according to claim 7, wherein the bias control signal (J47 and JB outputs) is coupled as an input to the biasing leg (J47 is connected to M7 gate and JB is connected to M6 gate).
In regard to Claim 9:
Noda discloses, in Figure 2, the amplifier according to claim 7, wherein the bias control signal (J47 and JB outputs) controls a potential at the biasing node (J67) in the biasing leg (4), coupled to the input terminal of the output amplifier stage (J67 coupled to M5 gate; Column 5: lines 32-36).
In regard to Claim 13:
Noda discloses, in Figure 2, an amplifier with bias stabilization, comprising:
a single-ended output transistor stage (M5) comprising an input terminal at a base of the transistor stage (M5 gate), the transistor stage being base-biased (Column 3: lines 9-11);
a biasing leg (4) comprising an input for the amplifier (M5, Column 3: lines 9-11) and a biasing node coupled to the input terminal of the output transistor stage (J47, JB connected to the gate of M5 via M6, M7); and
a bias feedback network (3) coupled between the input terminal of the output transistor stage (M5 gate) and the biasing leg (4).
In regard to Claim 14:
Noda discloses, in Figure 2, the amplifier according to claim 13, wherein the biasing leg (4) comprises a common collector input transistor (M6) and a common emitter biasing transistor (M7).
In regard to Claim 17:
Noda discloses, in Figure 2, the amplifier according to claim 13, wherein:
the bias feedback network (3) comprises a difference amplifier (M1-M4) and a reference voltage generator (2);
the difference amplifier (M1-M4) generates a bias control signal (J47, JB outputs) based on a difference between the input terminal (V1) of the output transistor stage (M5) and the reference voltage generator (2); and
the bias control signal (J47, JB) is coupled to the biasing node (J67) of the biasing leg (4).
In regard to Claim 18:
Noda discloses, in Figure 2, an amplifier with bias stabilization, comprising:
a single-ended output transistor stage (M5);
a biasing leg (4) comprising an input (Column 3: lines 9-11) for the amplifier (M5) and a biasing node (L67) coupled to an input terminal of the output transistor stage (M5 gate); and
a bias feedback network (3) coupled between the input terminal of the output transistor stage (M5 gate) and the biasing leg (4).
In regard to Claim 20:
Noda discloses, in Figure 2, the amplifier according to claim 18, wherein:
the bias feedback network (3) comprises a difference amplifier (M1-M4) and a reference voltage generator (2);
the difference amplifier (M1-M4) generates a bias control signal (J47 and JB outputs) based on a difference between the input terminal of the output transistor stage (M5 coupled to M2) and the reference voltage generator (2 coupled to M1); and
the bias control signal (J47 and Jb outputs) is coupled to the biasing node (J67) of the biasing leg (4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noda (US 8,471,548).
In regard to Claim 10:
All of the claim limitations have been discussed with respect to Claims 1 and 6-7 above, except for wherein an operating bandwidth of the difference amplifier is smaller than an operating bandwidth of the output amplifier stage. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have an operating bandwidth of the difference amplifier is smaller than an operating bandwidth of the output amplifier stage, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noda (US 8,471,548), in view of Aksin et al. (US 2018/0335509).
In regard to Claim 11:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein the output amplifier stage comprises a bipolar junction transistor.
Aksin discloses wherein the output amplifier stage comprises a bipolar junction transistor (¶ 0069).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the bipolar junction transistor taught by Aksin with the MOSFET amplifier circuit taught by Noda, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 12:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein the output amplifier stage comprises a base-biased bipolar junction transistor.
Aksin discloses wherein the output amplifier stage comprises a base-biased bipolar junction transistor (¶ 0069).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the base-biased bipolar junction transistor taught by Aksin with the MOSFET amplifier circuit taught by Noda, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Allowable Subject Matter
Claims 4-5, 15-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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