DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I (encompassing claims 1-11 and 14) in the reply filed on 5/12/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 1/25/24,2/7/24, 10/10/25, and 3/11/26. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the single accumulation section" in line 3. There is insufficient antecedent basis for this limitation in the claim. It is unclear to the examiner whether “the single accumulation section” in line 3 refers to “an accumulation section” in parent claim 3 or refers to a different accumulation section. For the purposes of examination, the examiner interprets “the single accumulation section” as - - the accumulation section - -. However, appropriate correction and/or clarification is requested.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-9, and 14 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (U.S. 2017/0179174 A1; “Yang”).
Regarding claim 1, Yang discloses a photodetector comprising:
A first semiconductor layer (200, Fig. 3) that includes a photoelectric conversion section (203, Fig. 3) and that has one surface serving as a light incident surface (S1, Fig. 3) and another surface serving as a first surface (S2, Fig. 3) ([0036]-[0037]);
A second semiconductor layer (206, 217, Fig. 3) that is stacked on the first surface and that includes a charge accumulation region (214, Fig. 3) ([0053]); and
A gate electrode (205, Fig. 3) that is adjacent to the second semiconductor layer through an insulating film (206, Fig. 3) and that allows formation of a channel (211, Fig. 3) extending in a stacking direction of the first semiconductor layer and the second semiconductor layer, between the photoelectric conversion section and the charge accumulation region ([0041]-[0042]).
Regarding claim 2, Yang discloses the charge accumulation region (214, Fig. 3) is provided at a position closer to a surface on a side opposite to a side of the first semiconductor layer (200, Fig. 3) of the second semiconductor layer (206, 217, Fig. 3).
Regarding claim 3, Yang discloses the second semiconductor layer (206, 217, Fig. 3) has a stacked structure in which a channel section (211, Fig. 3) and an accumulation section (214, Fig. 3) are stacked in this order from a side of the first semiconductor layer, and the charge accumulation region (214, Fig. 3) is provided only in the accumulation section (214, Fig. 3) among the channel section (211, Fig. 3) and the accumulation section (214, Fig. 3).
Regarding claim 4, Yang discloses a diameter of the channel section (211, Fig. 3) is smaller than a diameter of the accumulation section (214, Fig. 3).
Regarding claim 8, Yang discloses a combination of a material of the first semiconductor layer (200, Fig. 3), a material of the channel section (211, Fig. 3), and a material of the accumulation section (214, Fig. 3) includes a combination of group IV semiconductors ([0036], [0051], [0054]).
Regarding claim 9, Yang discloses the channel section includes multiple channel sections provided to be spaced apart from each other in plan view for the accumulation section ([0041]-[0042]).
Regarding claim 14, Yang discloses an electronic apparatus comprising:
A photodetector (Fig. 3);
An optical system configured to form an image of image light from an object on the photodetector ([0096]),
The photodetector comprising:
A first semiconductor layer (200, Fig. 3) that includes a photoelectric conversion section (203, Fig. 3) and that has one surface serving as a light incident surface (S1, Fig. 3) and another surface serving as a first surface (S2, Fig. 3) ([0036]-[0037]);
A second semiconductor layer (206, 217, Fig. 3) that is stacked on the first surface and that includes a charge accumulation region (214, Fig. 3) ([0053]); and
A gate electrode (205, Fig. 3) that is adjacent to the second semiconductor layer through an insulating film (206, Fig. 3) and that allows formation of a channel (211, Fig. 3) extending in a stacking direction of the first semiconductor layer and the second semiconductor layer, between the photoelectric conversion section and the charge accumulation region ([0041]-[0042]).
Claim(s) 1-3, 10-11, and 14 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitano (U.S. 2015/0029374 A1).
Regarding claim 1, Kitano discloses a photodetector comprising:
A first semiconductor layer (121, Fig. 1) that includes a photoelectric conversion section (111, Fig. 1) and that has one surface serving as a light incident surface and another surface serving as a first surface ([0066]);
A second semiconductor layer (125-126, 127, 128, Fig. 1) that is stacked on the first surface and that includes a charge accumulation region (124, Fig. 1) ([0066]-[0068]); and
A gate electrode (127, Fig. 1) that is adjacent to the second semiconductor layer through an insulating film (126, Fig. 1) and that allows formation of a channel (123, Fig. 1) extending in a stacking direction of the first semiconductor layer and the second semiconductor layer, between the photoelectric conversion section and the charge accumulation region ([0070]).
Regarding claim 2, Kitano discloses the charge accumulation region (124, Fig. 1) is provided at a position closer to a surface on a side opposite to a side of the first semiconductor layer (121, Fig. 1) of the second semiconductor layer (125-126, 127, 128, Fig. 1).
Regarding claim 3, Kitano discloses the second semiconductor layer (125-126, 127, 128, Fig. 1) has a stacked structure in which a channel section (123, Fig. 1) and an accumulation section (142, Fig. 1) are stacked in this order from a side of the first semiconductor layer, and the charge accumulation region (124, Fig. 1) is provided only in the accumulation section (142, Fig. 1) among the channel section and the accumulation section.
Regarding claim 10, Kitano discloses the gate electrode (127, Fig. 1, 6) surrounds the second semiconductor layer entirely in a circumferential direction in plan view ([0102]).
Regarding claim 11, Kitano discloses wherein each photoelectric conversion section is separated from another photoelectric conversion section by a separation region (112, Fig. 1), and the separation region includes at least either an insulating material or a semiconductor region into which an impurity has been injected ([0065]).
Regarding claim 14, Kitano discloses
A photodetector (Fig. 1);
An optical system configured to form an image of image light from an object on the photodetector ([0196]; Fig. 26),
The photodetector comprising:
A first semiconductor layer (121, Fig. 1) that includes a photoelectric conversion section (111, Fig. 1) and that has one surface serving as a light incident surface and another surface serving as a first surface ([0066]);
A second semiconductor layer (125-126, 127, 128, Fig. 1) that is stacked on the first surface and that includes a charge accumulation region (124, Fig. 1) ([0066]-[0068]); and
A gate electrode (127, Fig. 1) that is adjacent to the second semiconductor layer through an insulating film (126, Fig. 1) and that allows formation of a channel (123, Fig. 1) extending in a stacking direction of the first semiconductor layer and the second semiconductor layer, between the photoelectric conversion section and the charge accumulation region ([0070]).
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 6/4/2026
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