DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-11 are amended. Claims 1-11 are present for examination.
Response to Arguments
Applicant’s arguments, see pages 9-12, filed June 24, 2026, with respect to the 35 U.S.C. 103 rejections of claims 1 and 11 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Masuda (US 2019/0096948 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define
the amount of first through-vias (e.g. wherein the second semiconductor substrate includes a plurality of first through-vias, wherein the plurality of first through-vias are adjacent to each other in a horizontal direction).
the amount of second through-vias (e.g. wherein the support substrate includes a plurality of second through-vias, wherein the plurality of second through-vias are adjacent to each other in a horizontal direction).
The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 2022/0037382 A1) in view of Masuda (US 2019/0096948 A1).
Claim 1, Komai discloses a light detection device (image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62), comprising:
a first semiconductor substrate (solid state pickup element 120 is a first semiconductor substrate, hereinafter, first semiconductor substrate 120, [0438], Figs. 59 and 61) that includes a pixel portion (between through-electrodes 371/381 is a pixel portion, hereinafter, pixel portion, [0487], Figs. 59 and 61);
a second semiconductor substrate (logic circuit 122 and memory circuit 121 is formed on a second semiconductor substrate encapsulated in a dielectric material 133, hereinafter, second semiconductor substrate 121/122, [0486], Fig. 61) that includes a logic portion (second semiconductor substrate 122 includes a logic portion (i.e. logic circuit), [0486], Fig. 61) that has a signal processing circuit, wherein the signal processing circuit is configured to process a signal from the pixel portion (second semiconductor substrate 122 includes a signal processing circuit required for processing a signal from the pixel portion (i.e. logic circuit), [0486], Fig. 61); and
a support substrate (support board 132 is a support substrate, hereinafter, support substrate 132, [0140], Fig. 61) that includes a first wiring is formed (support substrate 132 includes the underlying dielectric layers 130 in which a first wiring is formed, [0438], Figs. 59 and 61),
the first semiconductor substrate 120, the second semiconductor substrate 121/122, and the support substrate 132 are stacked (first semiconductor substrate 120, the second semiconductor substrate 121/122, and the support substrate 132 are stacked, [0478], Fig. 59),
a first through-via (through-electrodes 381 is a first through-via, hereinafter, first through-via 381, [0462], Figs. 59 and 61) is in the second semiconductor substrate 121/122 (first through-via 381 is formed within the second semiconductor substrate 121/122, [0462], Figs. 59 and 61),
a second through-via (through-electrodes 371 is a second through-via, hereinafter, second through-via 371, [0475], Fig. 60) is in the support substrate 132 (second through-via 371 is formed in the support substrate 132, [0475], Fig. 60),
the first through-via 381 has a diameter smaller than that of the second through-via 371 (top diameter of the first through-via 381 is smaller than that of the bottom diameter of the second through-via 371, [0485], Fig. 60).
Komai does not explicitly disclose wherein each pixel of the plurality of pixels includes a photoelectric conversion element; and electrical connection between the first wiring in the support substrate and a second wiring in the second semiconductor substrate is through the first through-via and the second through-via.
However, Masuda discloses a first semiconductor substrate (Komai, solid state pickup element 120 is a first semiconductor substrate, hereinafter, first semiconductor substrate 120, [0438], Figs. 59 and 61; Masuda, Figs. 1, 2, and 6) that includes a pixel portion (between through-electrodes 371/381 is a pixel portion, hereinafter, pixel portion, [0487], Figs. 59 and 61) wherein each pixel of the plurality of pixels includes a photoelectric conversion element (Masuda, each pixel of the plurality of pixels within the pixel array unit 24 includes a photodiode PD which is a photoelectric conversion element, hereinafter, photoelectric conversion element PD, [0119], Figs. 1, 2, and 6; Komai, each pixel within the pixel portion includes a photoelectric conversion film 241 which is a photoelectric conversion element, hereinafter, photoelectric conversion element 241, , [0140], Fig. 59) and electrical connection between the first wiring in the support substrate and a second wiring in the second semiconductor substrate is through the first through-via and the second through-via (Masuda, multilayer wiring layer 102 is a first wiring, hereinafter, first wiring 102 and is in the upper structural body 11 which is a support substrate, hereinafter, support substrate 11 and a multilayer wiring layer 82 which is a second wiring, hereinafter, second wiring 82 in the lower structural body 12 which is a second semiconductor substrate, hereinafter, second semiconductor substrate 12 through the through-silicon-electrode 109 which is a first through-via, hereinafter, first through-via 109 and the through-chip-electrodes 105 which is a second through-via, hereinafter, second through-via 105, [0203], Fig. 6; Komai, electrical connection between wiring in the second semiconductor substrate 121/122 and the support substrate 132 is performed using a through-via, [0462], Figs. 55 and 60). The combination to utilize a photoelectric conversion element within each pixel of the plurality of pixels allows for converting the incident light into the electric signal and a plurality of pixel transistors that controls the photoelectric conversion operation and the reading operation of the photoelectrically converted electric signal (Masuda, [0112]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a photoelectric conversion element within each pixel of the plurality of pixels to allow for converting the incident light into the electric signal and a plurality of pixel transistors that controls the photoelectric conversion operation and the reading operation of the photoelectrically converted electric signal (Masuda, [0112]).
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Annotated Fig. 60 (Komai) - Illustrates the first through-via 381 having a diameter smaller than that of the second through-via 371 (i.e. top diameter of the first through-via 381 is smaller than that of the bottom diameter of the second through-via 371)
Claim 2, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 1.
Komai/Masuda discloses further comprising a wiring layer, wherein the wiring layer is between the second semiconductor substrate 121/122 and the support substrate 132 (Komai, a wiring layer is between the second semiconductor substrate 121/122 and the support substrate 132, [0487], Fig. 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6),
the second semiconductor substrate 121/122 is electrically connected to the wiring layer via the first through-via 381 (Komai, second semiconductor substrate 121/122 is electrically connected to the wiring layer via the first through-via 381, [0478], Figs. 59 and 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6), and
the support substrate 132 is electrically connected to the wiring layer via the second through-via 371 (Komai, support substrate 132 is electrically connected to the wiring layer via the second through-via 371, [0478], Figs. 59 and 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 3, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 1.
Komai/Masuda discloses further comprising a third semiconductor substrate, wherein the third semiconductor substrate (Komai, wiring layer 120b encapsulated in dielectric material 133 is a third semiconductor substrate, hereinafter, third semiconductor substrate 120b/133, [0479], Fig. 59; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) is stacked between the first semiconductor substrate 120 and the second semiconductor substrate 121/122 (Komai, third semiconductor substrate 120b/133 is stacked between the first semiconductor substrate 120 and the second semiconductor substrate 121/122, [0479], Fig. 59; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 4, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 3.
Komai/Masuda discloses further comprising a third through-via (Komai, through electrodes 391 is a third through-via, hereinafter, third through-via 391, [0479], Figs. 59 and 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) in the third semiconductor substrate 120b/133 (Komai, third through-via 391 is formed in the third semiconductor substrate 120b/133, [0479], Figs. 59 and 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6),
wherein a diameter of the third through-via 391 is smaller than a diameter of the second through-via 371 (Komai, diameter of the third through-via 391 is smaller than the bottom diameter of the second through-via 371, [0479], Figs. 55 and 59; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 5, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 3.
Komai/Masuda discloses further comprising a plurality of third semiconductor substrates, wherein the plurality of the third semiconductor substrates 120b/133 are stacked (Komai, third semiconductor substrate 120b/133, first semiconductor substrate 120, the second semiconductor substrate 121/122, and the support substrate 132 are stacked, [0478], Fig. 59; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 6, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 2.
Komai/Masuda discloses wherein the second semiconductor substrate 121/122 and the support substrate 132 are stacked together, and
the wiring layer and the second through-via 371 are stacked in the support substrate 132 in advance (Komai, wiring layer and the second through-via 371 are stacked in the support substrate 132 in advance, [0480], Figs. 58 and 59; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 7, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 2.
Komai/Masuda discloses wherein the second semiconductor substrate 121/122 and the support substrate 132 are stacked together,
in a case where the wiring layer is in the second semiconductor substrate 121/122, and
the second through-via 371 is in the support substrate 132 in advance (Komai, when the wiring layer is in the second semiconductor substrate 121/122, the second through-via 371 is formed in the support substrate 132 in advance, [0480], Figs. 58 and 59; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 8, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 1.
Komai/Masuda discloses wherein a width of the second semiconductor substrate 121/122 is narrower than a width of the first semiconductor substrate 120 (Komai, second semiconductor substrate 121/122 has a width narrower than that of the first semiconductor substrate 120, [0487], Fig. 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 9, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 1.
Komai/Masuda discloses wherein the support substrate 132 does not have a circuit element therein (Komai, support substrate 132 does not have a circuit element therein, [0140], Fig. 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 10, Komai/Masuda discloses the light detection device (Komai, image pickup apparatus 501 includes a light detection device, [0491], Figs. 59-62; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6) according to claim 2.
Komai/Masuda discloses wherein the wiring layer is a re-distribution layer (Komai, wiring layer includes communication wires T and is a re-distribution layer, [0346], Fig. 61; Masuda, solid-state image pickup device 1, [0112], Figs. 1, 2, and 6).
Claim 11, Komai discloses an electronic apparatus (image pickup apparatus 501, [0491], Figs. 59 and 61-62) comprising:
a light detection device (image pickup apparatus 501 is equipped with a light detection device, [0491], Figs. 59 and 61-62) including:
a first semiconductor substrate (solid state pickup element 120 is a first semiconductor substrate, hereinafter, first semiconductor substrate 120, [0438], Figs. 59 and 61) that includes a pixel portion (between through-electrodes 371/381 is a pixel portion, hereinafter, pixel portion, [0487], Figs. 59 and 61);
a second semiconductor substrate (logic circuit 122 and memory circuit 121 is formed on a second semiconductor substrate encapsulated in a dielectric material 133, hereinafter, second semiconductor substrate 121/122, [0486], Fig. 61) that includes a logic portion (second semiconductor substrate 122 includes a logic portion (i.e. logic circuit), [0486], Fig. 61) that has a signal processing circuit, wherein the signal processing circuit is configured to process a signal from the pixel portion (second semiconductor substrate 122 includes a signal processing circuit required for processing a signal from the pixel portion (i.e. logic circuit), [0486], Fig. 61); and
a support substrate (support board 132 is a support substrate, hereinafter, support substrate 132, [0140], Fig. 61) that includes a first wiring is formed (support substrate 132 includes the underlying dielectric layers 130 in which wiring is formed, [0438], Figs. 59 and 61), wherein
the first semiconductor substrate 120, the second semiconductor substrate 121/122, and the support substrate 132 are stacked (first semiconductor substrate 120, the second semiconductor substrate 121/122, and the support substrate 132 are stacked, [0478], Fig. 59),
a first through-via (through-electrodes 381 is a first through-via, hereinafter, first through-via 381, [0462], Figs. 59 and 61) is in the second semiconductor substrate 121/122 (first through-via 381 is within the second semiconductor substrate 121/122, [0462], Figs. 59 and 61),
a second through-via (through-electrodes 371 is a second through-via, hereinafter, second through-via 371, [0475], Fig. 60) is in the support substrate 132 (second through-via 371 is in the support substrate 132, [0475], Fig. 60),
the first through-via 381 has a diameter smaller than that of the second through-via 371 (top diameter of the first through-via 381 is smaller than that of the bottom diameter of the second through-via 371, [0485], Fig. 60).
Komai does not explicitly disclose wherein each pixel of the plurality of pixels includes a photoelectric conversion element; and electrical connection between the first wiring in the support substrate and a second wiring in the second semiconductor substrate is through the first through-via and the second through-via.
However, Masuda discloses a first semiconductor substrate (Komai, solid state pickup element 120 is a first semiconductor substrate, hereinafter, first semiconductor substrate 120, [0438], Figs. 59 and 61; Masuda, Figs. 1, 2, and 6) that includes a pixel portion (between through-electrodes 371/381 is a pixel portion, hereinafter, pixel portion, [0487], Figs. 59 and 61) wherein each pixel of the plurality of pixels includes a photoelectric conversion element (Masuda, each pixel of the plurality of pixels within the pixel array unit 24 includes a photodiode PD which is a photoelectric conversion element, hereinafter, photoelectric conversion element PD, [0119], Figs. 1, 2, and 6; Komai, each pixel within the pixel portion includes a photoelectric conversion film 241 which is a photoelectric conversion element, hereinafter, photoelectric conversion element 241, , [0140], Fig. 59) and electrical connection between the first wiring in the support substrate and a second wiring in the second semiconductor substrate is through the first through-via and the second through-via (Masuda, multilayer wiring layer 102 is a first wiring, hereinafter, first wiring 102 and is in the upper structural body 11 which is a support substrate, hereinafter, support substrate 11 and a multilayer wiring layer 82 which is a second wiring, hereinafter, second wiring 82 in the lower structural body 12 which is a second semiconductor substrate, hereinafter, second semiconductor substrate 12 through the through-silicon-electrode 109 which is a first through-via, hereinafter, first through-via 109 and the through-chip-electrodes 105 which is a second through-via, hereinafter, second through-via 105, [0203], Fig. 6; Komai, electrical connection between wiring in the second semiconductor substrate 121/122 and the support substrate 132 is performed using a through-via, [0462], Figs. 55 and 60). The combination to utilize a photoelectric conversion element within each pixel of the plurality of pixels allows for converting the incident light into the electric signal and a plurality of pixel transistors that controls the photoelectric conversion operation and the reading operation of the photoelectrically converted electric signal (Masuda, [0112]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a photoelectric conversion element within each pixel of the plurality of pixels to allow for converting the incident light into the electric signal and a plurality of pixel transistors that controls the photoelectric conversion operation and the reading operation of the photoelectrically converted electric signal (Masuda, [0112]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sukegawa (US 2013/0062504 A1) discloses a light detection device, comprising a first semiconductor substrate (first chip (CIS chip) 11 is a first semiconductor substrate, hereinafter, first semiconductor substrate 11, [0129], Fig. 8) that includes a pixel portion in which a plurality of pixels (circuit area 231 denotes a pixel portion (i.e. unit pixel) in which a plurality of pixels are oriented, [0129], Fig. 8) each including a photoelectric conversion element are arranged (unit pixel has a photoelectric conversion element, [0082], Fig. 8);
a second semiconductor substrate (second chip (logic chip) 12 is a second semiconductor substrate, hereinafter, second semiconductor substrate 12, [0112], Fig. 8); and
a support substrate (support substrate 13, [0112], Fig. 8) in which wiring is formed,
the first semiconductor substrate 11, the second semiconductor substrate 12, and the support substrate 13 being stacked (first semiconductor substrate 11, the second semiconductor substrate 12, and the support substrate 13 being stacked, [0113], Fig. 8),
wherein electrical connection between wiring in the second semiconductor substrate 12 and the support substrate 13 is performed using a through-via (electrical connection between wiring in the second semiconductor substrate 12 and the support substrate 13 is performed using a through-via 14/242, [0125], Fig. 8),
a first through-via (through-VIAs 14 is a first through-via, hereinafter, first through-via 14, [0069], Fig. 8) is formed in the second semiconductor substrate 12 (first through-via 14 is formed in the second semiconductor substrate 12, [0069], Fig. 8),
a second through-via (through-via 242 is a second through-via, hereafter, second through-via 242, [0125], Fig. 8) is formed in the support substrate 13 (second through-via 242 is formed in the support substrate 13, [0125], Fig. 8), and
the first through-via 14 having a diameter smaller than that of the second through-via 242 (first through-via 14 having a diameter smaller than that of the second through-via 242, [0069], Fig. 8).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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