DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 1/26/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7, and 12 is/are rejected under 35 U.S.C. 102(a)(1), or alternatively 35 U.S.C. 102(a)(2) as being anticipated by Ito et al. (WO 2021/107145 A1; references to U.S. 2022/0399380 as English translation; “Ito”).
Regarding claim 1, Ito discloses a pixel assembly, comprising:
An insulating substrate (10, Fig. 5B) including a first surface and a second surface on an opposite side to the first surface ([0053]);
A drive transistor (35, Fig. 5B) in the insulating substrate or on the first surface, the drive transistor including a source electrode (35b, Fig. 5B) and a drain electrode (35a, Fig. 5B) ([0076]-[0077]);
A power feeder (4, Fig. 1B) connectable to an external power supply ([0035]-[0036]);
A connection conductor layer (5, Fig. 5B) on the insulating substrate, the connection conductor layer connecting the source electrode to the power feeder ([0038], [0051]); and
A light emitter (31, Fig. 5B) on the second surface, the light emitter being electrically connected to the drain electrode (35a, Fig. 5B) ([0033]),
Wherein the connection conductor layer (5, Fig. 5B) includes a surrounding portion (57, Fig. 5B-5C) surrounding the light emitter in a plan view on the second surface ([0051]).
Regarding claim 2, Ito discloses the pixel assembly comprises a plurality of pixels arranged in a matrix wherein each pixel comprises a light emitter (31, Fig. 5B) and a surrounding portion (57, Fig. 5B-5C) (Fig. 1A; [0027], [0032]-[0034]).
Regarding claim 7, Ito discloses a pixel assembly, comprising:
An insulating substrate (10, Fig. 5B) including a first surface and a second surface on an opposite side to the first surface ([0053]);
A drive transistor (35, Fig. 5B) in the insulating substrate or on the first surface, the drive transistor including a source electrode (35b, Fig. 5B) and a drain electrode (35a, Fig. 5B) ([0076]-[0077]);
A power feeder (4, Fig. 1B) connectable to an external power supply ([0035]-[0036]);
A connection conductor layer (5, Fig. 5B) on the insulating substrate, the connection conductor layer connecting the source electrode to the power feeder ([0038], [0051]); and
A light emitter (31, Fig. 5B) on the second surface, the light emitter electrically connected to the drain electrode ([0033]),
Wherein the connection conductor layer (5, Fig. 5B) includes a planar portion (57, Fig. 5B) on the second surface ([0051]).
Regarding claim 12, Ito discloses a pixel assembly, comprising:
An insulating substrate (10, 15, 16, Fig. 5B) including a first surface and a second surface on an opposite side to the first surface, the insulating substrate including a recess (between adjacent portions of 16, Fig. 5B) on the second surface ([0053]);
A drive transistor (35, Fig. 5B) in the insulating substrate or on the first surface, the drive transistor including a source electrode (35b, Fig. 5B) and a drain electrode (35a, Fig. 5B) ([0076]-[0077]);
A power feeder (4, Fig. 1B) connectable to an external power supply;
A connection conductor layer (5, Fig. 5B) on the insulating substrate, the connection conductor layer connecting the source electrode to the power feeder ([0038], [0051]); and
A light emitter (31, Fig. 5B) in the recess (between adjacent portions of 16, Fig. 5B), the light emitter being electrically connected to the drain electrode ([0033]),
Wherein the connection conductor layer (5, Fig. 5B) includes at least one of a surrounding portion surrounding the light emitter in a plan view or a planar portion (57, Fig. 5B) on the second surface ([0051]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 6, 8-9, 11, 13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (WO 2021/107145 A1; references to U.S. 2022/0399380 as English translation; “Ito”) as applied to claims 1, 7, and 12 above.
Regarding claim 3, Ito discloses a surrounding portion (57, Fig. 5B-5C) and a surrounded portion (portion containing 31, Fig. 5B), wherein the surrounding portion and surrounded portions are formed in a plurality within a display device ([0027], [0032]-[0034]). Yet, Ito does not disclose the plurality of surrounding portions has a larger area than that of the plurality of surrounded portions. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select the relative areas of the plurality of surrounding portions to be larger than that of the surrounded portions, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 6, Ito discloses the drive transistor (35, Fig. 5B) is an n-channel thin-film transistor ([0077]), the power feeder (4, Fig. 1B) includes a first power feeder to which a first power supply voltage is applied and a second power feeder to which a second power supply voltage lower than the first power supply voltage is applied ([0035]). Yet, Ito does not disclose the source electrode is necessarily connected to the second power feeder between the first power feeder and the second power feeder. However, one of ordinary skill in the art would have recognized the finite number of predictable solutions for connecting the source electrode to a power feeder comprising a first power feeder and a second power feeder. Thus, it would have been obvious to have the source electrode connected to the second power feeder since it has been held that it is obvious to try from a finite number of identified, predictable solutions with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 8, Ito discloses a planar portion (57, Fig. 5B) but does not disclose its area is at least half an area of the second surface. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select the relative area of the planar portion to be at least half an area of the second surface, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 9, Ito discloses the connection conductor layer (5, Fig. 5B) is at a height different from a height at which the light emitter (31, Fig. 5B) is located on the second surface.
Regarding claim 11, Ito discloses the drive transistor (35, Fig. 5B) is an n-channel thin-film transistor ([0077]), the power feeder (4, Fig. 1B) includes a first power feeder to which a first power supply voltage is applied and a second power feeder to which a second power supply voltage lower than the first power supply voltage is applied ([0035]). Yet, Ito does not disclose the source electrode is necessarily connected to the second power feeder between the first power feeder and the second power feeder. However, one of ordinary skill in the art would have recognized the finite number of predictable solutions for connecting the source electrode to a power feeder comprising a first power feeder and a second power feeder. Thus, it would have been obvious to have the source electrode connected to the second power feeder since it has been held that it is obvious to try from a finite number of identified, predictable solutions with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 13, Ito discloses the at least one of the surrounding portion or the planar portion (57, Fig. 5B) is a conductor portion ([0051]) but does not disclose the conductor portion has an area being at least a half area of the second surface. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select the relative area of the surrounding portion or the planar portion to be at least half an area of the second surface, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 15, Ito discloses the drive transistor (35, Fig. 5B) is an n-channel thin-film transistor ([0077]), the power feeder (4, Fig. 1B) includes a first power feeder to which a first power supply voltage is applied and a second power feeder to which a second power supply voltage lower than the first power supply voltage is applied ([0035]). Yet, Ito does not disclose the source electrode is necessarily connected to the second power feeder between the first power feeder and the second power feeder. However, one of ordinary skill in the art would have recognized the finite number of predictable solutions for connecting the source electrode to a power feeder comprising a first power feeder and a second power feeder. Thus, it would have been obvious to have the source electrode connected to the second power feeder since it has been held that it is obvious to try from a finite number of identified, predictable solutions with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 5, 10, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (WO 2021/107145 A1; references to U.S. 2022/0399380 as English translation; “Ito”) as applied to claims 1, 7, and 12 above, and further in view of Fan et al. (U.S. 2015/0084054 A1; “Fan”).
Regarding claims 5, 10, and 14, Ito discloses the drive transistor (35, Fig. 5B) is an n-channel thin-film transistor ([0077]), the power feeder (4, Fig. 1B) includes a first power feeder to which a first power supply voltage is applied and a second power feeder to which a second power supply voltage lower than the first power supply voltage is applied ([0035]). Yet, Ito does not disclose the following:
The drive transistor is a p-channel thin-film transistor;
The source electrode is necessarily connected to the first power feeder between the first power feeder and the second power feeder.
Regarding (a), Fan discloses a drive transistor may be a n-channel thin-film transistor or a p-channel thin-film transistor ([0033]). Because both Ito and Fan teach methods of forming drive transistors, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of the drive transistor being a p-channel thin-film transistor. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding (b), one of ordinary skill in the art would have recognized the finite number of predictable solutions for connecting the source electrode to a power feeder comprising a first power feeder and a second power feeder. Thus, it would have been obvious to have the source electrode connected to the first power feeder since it has been held that it is obvious to try from a finite number of identified, predictable solutions with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (WO 2021/107145 A1; references to U.S. 2022/0399380 as English translation; “Ito”) as applied to claim 1 above, and further in view of Yokoyama et al. (U.S. 2020/0135126 A1; “Yokoyama”).
Regarding claim 16, Ito discloses the pixel assembly according to claim 1 (see claim 1 rejection above) and a substrate (2, Fig. 5B) including one main (top) surface receiving the pixel assembly and another main (bottom) surface, the other main surface being on an opposite side to the one main surface. Yet, Ito does not disclose receiving a drive configured to drive the light emitter on the other main surface. However, Yokoyama discloses receiving a drive (6, Fig. 1) configured to drive a light emitter (14, Fig. 1), wherein the light emitter is on the one main (top surface), and the drive is on the other main (bottom) surface of a substrate (1, Fig. 1) ([0035]). This has the advantage of reducing the dimensions of the overall display device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Ito with a drive configured to drive the light emitter on the other main surface of the substrate, as taught by Yokoyama, so as to reduce overall dimensions.
Regarding claim 17, Ito and Yokoyama disclose the substrate includes a side surface connecting the one main surface and the other main surface, and wherein the display device comprises side wiring (Yokoyama: 30, Fig. 1) electrically connecting the pixel assembly and the drive (Yokoyama: 6, Fig. 1) on the side surface.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812
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