Prosecution Insights
Last updated: October 02, 2026
Application No. 18/293,371

Display Substrate and Display Apparatus

Non-Final OA §103
Filed
Jan 30, 2024
Priority
Sep 09, 2022 — nonprovisional of PCTCN2022118241
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
701 granted / 821 resolved
+17.4% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
26 currently pending
Career history
830
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.3%
+22.3% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 2024/0212597 A1 in view of Fang US 2024/0019969 A1. Regarding claims 1 and 17, Wang discloses: A display substrate (Figs. 1-8), comprising a display region (Fig. 1; 100) and a bonding region (Fig. 6; 200) connected with the display region, wherein the display region comprises a plurality of data signal lines (Fig. 7; 42) and K rows and L columns of sub-pixels (Figs. 1 and 2; Pxij), both K and L are positive integers greater than 1; a plurality of first spaces (Fig. 2; spaces shown between sub-pixels P in horizontal direction) are comprised between K sub-pixel rows and a plurality of second spaces (Fig. 2; spaces shown between sub-pixels P in vertical direction) are comprised between L sub-pixel columns, wherein a first space is located between two adjacent sub-pixel rows, a second space is located between two adjacent sub-pixel columns, on a plane parallel to the display substrate, a first data connection line (Fig. 7; 50 horizontal) extends along a first direction, the second data connection line (Fig. 7; 50 vertical) extends along a second direction, and the first direction intersects with the second direction; one end of the first data connection line (Fig. 7; horizontal) is electrically connected with one of the data signal lines (Fig. 7; 42), and the other end is electrically connected with one of second data connection lines (Fig. 7; 50 vertical); one end of the second data connection line (Fig. 7; vertical) is electrically connected with the first data connection line (Fig. 7; 50 horizontal), and the other end is electrically connected with the bonding region (Fig. 6/7; 60 in 200). Wang does not disclose: at least one first space is provided with a first data connection line, at least one second space is provided with at least one second data connection line. Fang discloses a publication from a similar field of endeavor in which: at least one first space (spaces shown between pixel regions 140) is provided with a first data connection line (130), at least one second space (spaces shown between pixel regions 140) is provided with at least one second data connection line (130) (Fig. 4). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to distribute the data signal and connection lines of Wang within the spaces between adjacent sub-pixel/sensor regions as shown by Fang to improve display efficiency/performance similar to improving the touch capacitance of the sensor pixels noted by Fang (para 0015). Regarding claim 4, although Wang/Fang do not specifically disclose “wherein in a same second space, a quantity of the second data connection lines is three, and the three second data connection lines are respectively connected with three different first data connection lines”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine multiples of the first/second data connection lines of Wang since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co., v. Bemis Co., 193 USPQ 8. Allowable Subject Matter Claims 2, 3, 5-16 are 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 2 stating “wherein the first space is further provided with a fourth data connection line and the second space is further provided with a third data connection line; a same second space is provided with at least one second data connection line and at least one third data connection line; the fourth data connection line extends along the first direction, one end is electrically connected with a data signal line, and the other end is connected with the third data connection line; the third data connection line extends along the second direction, one end is connected with the fourth data connection line, and the other end is electrically connected with the bonding region; wherein the first data connection line and the second data connection line are connected through a via, and the third data connection line and the fourth data connection line are of an integrally formed structure”; and of claim 5 stating “wherein at least one sub-pixel comprises a pixel drive circuit, in a plane perpendicular to the display substrate, the display substrate comprises a base substrate, and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer which are sequentially stacked on the base substrate; the first semiconductor layer comprises: active layers of a plurality of low temperature poly silicon transistors located in the pixel drive circuit; the first conductive layer comprises: control electrodes of the plurality of poly silicon transistors and a first electrode plate of a storage capacitor located in the pixel drive circuit; the second conductive layer comprises: a second electrode plate of the storage capacitor located in the pixel drive circuit; the second semiconductor layer comprises: active layers of a plurality of oxide transistors located in the pixel drive circuit; the third conductive layer comprises: control electrodes of the plurality of oxide transistors located in the pixel drive circuit; the fourth conductive layer comprises the first data connection line, and first electrodes and second electrodes of the plurality of low temperature poly silicon transistors and first electrodes and second electrodes of the plurality of oxide transistors located in the pixel drive circuit; and the fifth conductive layer comprises a data signal line, a first power supply line, and the second data connection line”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Jan 30, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.8%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

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