Prosecution Insights
Last updated: August 16, 2026
Application No. 18/293,460

SILICON CARBIDE SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Jan 30, 2024
Priority
Sep 15, 2021 — JP 2021-150122 +1 more
Examiner
FAN, SU JYA
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sumitomo Electric Industries Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
716 granted / 946 resolved
+7.7% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
37 currently pending
Career history
1002
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
50.5%
+10.5% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
19.9%
-20.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 946 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant's election with traverse of Species A, claims 1-14, in the reply filed on 5/29/26 is acknowledged. Upon reconsideration, the restriction requirement of 4/28/26 is withdrawn. In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01. Allowable Subject Matter Claims 3-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tominaga et al., US Publication No. 2023/0155021 A1. Tominaga anticipates: A silicon carbide semiconductor device comprising (see figs. 1-6): PNG media_image1.png 452 602 media_image1.png Greyscale a silicon carbide substrate (1) having a first principal surface; an interlayer insulating film (29) covering the first principal surface; and a gate pad (102) and a source pad (101) provided on the interlayer insulating film, wherein the silicon carbide substrate includes, in plan view in a direction perpendicular to the first principal surface, a first region including a plurality of unit cells (CR), a second region overlapping the gate pad (102/103), and a third region (e.g. third region annotated) contiguous to the second region, wherein each of the plurality of unit cells (CR) includes a drift region (2) having a first conductive type (n type), a body region (3) having a second conductive type (p type) different from the first conductive type, a source region (5) provided on the first principal surface, separated from the drift region by the body region, and having the first conductive type (n type), a contact region (6) provided on the first principal surface, electrically connected to the body region, and having the second conductive type (p type), a gate electrode (9) electrically connected to the gate pad (102/103), and a gate insulating film (8) provided between the gate electrode and the drift region, the body region, and the source region, wherein the second region (e.g. overlapping 102) includes a first semiconductor region (e.g. 13 below 102 in fig. 4) having the second conductive type (p type), wherein the third region (e.g. third region annotated) includes a second semiconductor region (e.g. 13 below 17) having the second conductive type (p type), wherein the first semiconductor region (e.g. 13 below 102) and the second semiconductor region (e.g. 13 below 17) are contiguous to each other on the first principal surface, wherein, in the interlayer insulation film (29), a first contact hole (7) reaching the source region (5) and the contact region (6/16, e.g. 6 is first well contact and 16 is second well contact), and a second contact hole (17) reaching the second semiconductor region (e.g. 13 below 17) are formed, and wherein the source pad (101) is electrically connected to the source region (5) and the contact region (6/16) via the first contact hole (7), electrically connected to the second semiconductor region (e.g. 13 below 17) via the second contact hole (17), and in a cross section as viewed in a direction parallel to the first principal surface, a dimension in a short direction of the second contact hole (17) is greater than a dimension in a short direction of the first contact hole (7). See Tominaga at para. [0001] – [0116], figs. 1-23. 2. The silicon carbide semiconductor device as claimed in claim 1, wherein the contact region (6/16) and the second semiconductor region (e.g. 13 below 17) are contiguous to each other on the first principal surface, fig.4. Relevant Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Hayashi, US 20150206967 A1 (e.g. In fig. 1B, Hayashi teaches contact holes of different widths.) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 30 July 2026
Read full office action

Prosecution Timeline

Jan 30, 2024
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
87%
With Interview (+11.1%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 946 resolved cases by this examiner. Grant probability derived from career allowance rate.

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