DETAILED ACTION
Specification
The Specification amendments have been approved and entered into the record.
Election/Restrictions
Applicant’s election of Group I and Species 1a, 2a, and 3a, corresponding to claims 1, 3-5, 10-11, 13, 17-19, in the reply filed on 8/25/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Rejection over Horio et al., US 2005/0281303
Claim(s) 1 and 18 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Horio et al., US 2005/0281303.
Regarding claim 1, Horio (figures 1C & 2B) teaches a light emitting diode chip, comprising:
a base substrate 100; and
at least two light emitting structures arranged on the base substrate 100, wherein orthographic projections of the at least two light emitting structures on the base substrate 100 are spaced apart, and the at least two light emitting structures are sequentially connected in series (by 104),
wherein at least one of the light emitting structures comprises:
a first semiconductor layer 101 arranged on the base substrate 100;
a light emitting layer 102 arranged on a side of the first semiconductor layer 101 away from the base substrate 100;
a second semiconductor layer 103 arranged on a side of the light emitting layer 102 away from the base substrate 100;
a first insulation layer 106 arranged on a side of the second semiconductor layer 103 away from the base substrate 100;
a current spreading layer 105 arranged on a side of the first insulation layer 106 away from the base substrate 100; and
a first electrode 115 arranged on a side of the current spreading layer 105 away from the base substrate 100,
wherein the at least one light emitting structure comprises a first via hole (filled by 105) located in the first insulation layer 106, the first electrode 115 is electrically connected to the current spreading layer 105, and the current spreading layer 105 is electrically connected to the second semiconductor layer 103 through the first via hole (filled by 105); and
wherein an orthographic projection of the first via hole (filled by 105) on the base substrate 100 falls within an orthographic projection of the current spreading layer 105 on the base substrate 100, and the orthographic projection of the current spreading layer 105 on the base substrate 100 falls within an orthographic projection of the second semiconductor layer 103 on the base substrate 100.
With respect to claim 18, Horio (figures 2A-B) the light emitting diode chip comprises three or more light emitting structures, each of the light emitting structures comprises the first via hole (filled by 105) located in the first insulation layer 106, the first electrode 115 is electrically connected to the current spreading layer 105, and the current spreading layer 105 is electrically connected to the second semiconductor layer 103 through the first via hole (filled by 105); and wherein the orthographic projection of the first via hole (filled by 105) on the base substrate 100 falls within the orthographic projection of the current spreading layer 105 on the base substrate 100, and the orthographic projection of the current spreading layer 105 on the base substrate 100 falls within the orthographic projection of the second semiconductor layer 103 on the base substrate 100.
Rejection over Sun et al., CN 114420817
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 10-11, 13, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al., CN 114420817, in view of Horio et al/. US 2005/0281303.
Regarding claim 1, Sun (figure 3) teaches a light emitting diode chip, comprising:
a base substrate 30; and
at least two light emitting structures arranged on the base substrate 30, wherein orthographic projections of the at least two light emitting structures on the base substrate 30 are spaced apart, and the at least two light emitting structures are sequentially connected in series (through 62),
wherein at least one of the light emitting structures comprises:
a first semiconductor layer 411 arranged on the base substrate 30;
a light emitting layer 412 arranged on a side of the first semiconductor layer 411 away from the base substrate 30;
a second semiconductor layer 413 arranged on a side of the light emitting layer 412 away from the base substrate 30;
a current spreading layer 61; and
a first electrode 91 arranged on a side of the current spreading layer 61 away from the base substrate 30, and
the orthographic projection of the current spreading layer 61 on the base substrate 30 falls within an orthographic projection of the second semiconductor layer 413 on the base substrate 30.
Sun fails to teach a first insulation layer arranged on a side of the second semiconductor layer away from the base substrate; and wherein the at least one light emitting structure comprises a first via hole located in the first insulation layer, the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via hole; and wherein an orthographic projection of the first via hole on the base substrate falls within an orthographic projection of the current spreading layer on the base substrate; and the current spreading layer arranged on a side of the first insulation layer away from the base substrate.
Horio (figures 1C & 2B) teaches a first insulation layer 106 arranged on a side of the second semiconductor layer 103 away from the base substrate 100; and wherein the at least one light emitting structure comprises a first via hole (filled by 105) located in the first insulation layer 106, the first electrode 115 is electrically connected to the current spreading layer 105, and the current spreading layer 105 is electrically connected to the second semiconductor layer 103 through the first via hole (filled by 105); and wherein an orthographic projection of the first via hole (filled by 105) on the base substrate 100 falls within an orthographic projection of the current spreading layer 105 on the base substrate 100; and though the current spreading layer 105 is not arranged on a side of the first insulation layer 106 away from the base substrate 100.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the first insulation layer of Horio in the invention of Sun because Horio teaches it is a protection layer.
With respect to claim 3, Sun teaches a bridging conductive portion 62 arranged on a side of the current spreading layer 61 away from the base substrate 30, and the bridging conductive portion 62 comprises a first part and a second part; and wherein the at least two light emitting structures comprise a first light emitting structure 42 and a second light emitting structure 41 that are adjacent to each other, the first light emitting structure 42 and the second light emitting structure 41 are electrically connected through the bridging conductive portion 62, the first part of the bridging conductive portion 62 is electrically connected to the second semiconductor layer 423 of the first light emitting structure 42, the second part of the bridging conductive portion 62 is electrically connected to the first semiconductor layer 411 of the second light emitting structure 41, an orthographic projection of the first part of the bridging conductive portion 62 on the base substrate 30 falls within an orthographic projection of the second semiconductor layer 423 of the first light emitting structure 42 on the base substrate, and an orthographic projection of the second part of the bridging conductive portion 62 on the base substrate 30 falls within an orthographic projection of the first semiconductor layer 411 of the second light emitting structure 41 on the base substrate 30.
As to claim 4, Sun (figure 3) teaches the orthographic projection of the first part of the bridging conductive portion 62 on the base substrate 30 overlaps at least partially with an orthographic projection of the current spreading layer 25 of the first light emitting structure 42 on the base substrate 30.
In re claim 5, Horio teaches the orthographic projection of the first via hole filled by 105) on the base substrate 100 overlaps at least partially with the orthographic projection of the first part of the bridging conductive portion 62 on the base substrate 30 of Sun.
Concerning claim 10, Sun (figure 3) teaches the light emitting diode chip further comprises a second reflection layer 53 on a side of the current spreading layer 61 away from the base substrate 30, and the second reflection layer 53 comprises a Bragg reflector.
Pertaining to claim 11, the light emitting diode chip further comprises a second via hole filled by 91 in the second reflection layer 53, the first electrode 91 is electrically connected to the current spreading layer 61 through the second via hole (filled by 91), and the orthographic projection of the first via hole (Hori:filled by 105) on the base substrate 30 falls within an orthographic projection of the second via hole (filled by 91) on the base substrate 30.
Pertaining to claim 13, though Sun fails to teach in one and same light emitting structure of the at least one light emitting structure, a ratio of an area of the orthographic projection of the current spreading layer on the base substrate to an area of the orthographic projection of the second semiconductor layer on the base substrate is less than 0.1, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the ratio through routine experimentation (MPEP 2144.05).
In claim 17, Sun (figure 3) teaches the light emitting diode chip further comprises a second electrode 92 and a third via hole (filled by 92), the third via hole (filled by 92) is located in the second reflection layer 53, the second electrode 92 is electrically connected (through 63) to the first semiconductor layer 421 of one light emitting structure through the third via hole (filled by 92), and an orthographic projection of the third via hole (filled by 92) on the base substrate 30is spaced apart from the orthographic projection of the first via hole (filled by 91) on the base substrate 30.
Regarding claim 18, though Sun fails to teach the light emitting diode chip comprises three or more light emitting structures, each of the light emitting structures comprises the first via hole located in the first insulation layer, the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via hole; and wherein the orthographic projection of the first via hole on the base substrate falls within the orthographic projection of the current spreading layer on the base substrate, and the orthographic projection of the current spreading layer on the base substrate falls within the orthographic projection of the second semiconductor layer on the base substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use three or more light emitting structures in the invention of Sun because teaches the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)), such as Horio teaches in figure 2A).
With respect to claim 19, Sun (abstract) teaches a display device, comprising the light emitting diode chip of claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teaches various aspects of the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 8/31/26
Prosecution Insights