DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-8 & 10 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Kumakura et al. (US Patent 10,020,373).
Regarding claim 1, Kumakura teaches a semiconductor device 2 comprising:
a substrate 11(10) having a first principal surface (top surface, Fig. 2);
an electrode 21(120) provided above the first principal surface (Fig. 2);
a plating layer provided on the electrode (Kumakura teaches a plating layer on the first electrode layer 21 in column 5, lines 12-14 – because the plating layer is formed directly on the wiring layer 22, it is understood to have the shape of the wiring layer 22, Fig. 2);
a first passivation layer 31 provided on the first principal surface, covering a portion of the electrode 21(120) and containing an inorganic material (SiN) (Fig. 2 and associated text); and
a second passivation layer (33 or 33 & 32) provided on the first passivation layer 31, covering a portion of the plating layer (because the plating layer has the shape of the wiring layer 22, it is understood that the second passivation layer covers a portion of the plating layer which is directly on the wiring layer, see Fig. 2), and containing an organic material (e.g. polyimide) (see Fig. 2 and associated text), wherein
a first opening is formed in the first passivation layer 31 to expose a portion of the electrode (note the opening occupied by electrode 21(120) in Fig. 2),
a second opening is formed in the second passivation layer 33 so as to be continuous with the first opening (note the opening occupied by electrode 22(120) in Fig. 2), and
a second sidewall surface of the second opening is located inside a first sidewall surface of the first opening (see Fig. 2).
Regarding claim 3, Kumakura teaches the semiconductor device as claimed in claim 1, wherein a portion of a lower surface of the first passivation layer 31 makes contact with an upper surface of the electrode 21(120) (Fig. 2).
Regarding claim 4, Kumakura teaches the semiconductor device as claimed in claim 1, wherein a thickness of the first passivation layer is greater than or equal to 0.2 um and less than or equal to 1.0 um (column 6, lines 35-40).
Regarding claim 6, Kumakura teaches the semiconductor device as claimed in claim 1, wherein the first passivation layer 31 includes a silicon nitride layer (Fig. 2).
Regarding claim 7, Kumakura teaches the semiconductor device as claimed in claim 1, wherein the second passivation layer 33 includes a polyimide layer (Fig. 2).
Regarding claim 8, Kumakura teaches the semiconductor device as claimed in claim 1, wherein the substrate is a silicon carbide substrate (column 4, lines 37-38).
Regarding claim 10, Kumakura teaches the semiconductor device as claimed in claim 1, further comprising: an ohmic layer provided between the first principal surface of the substrate and the electrode (column 10, lines 21-23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kumakura as applied to claim 1 above.
Regarding claim 2, Kumakura does not expressly teach the semiconductor device as claimed in claim 1, wherein in a cross section perpendicular to the first principal surface and the first side wall surface, a maximum value of a distance between the first sidewall surface and the second sidewall surface in a direction parallel to the first principal surface is greater than or equal to 1um and less than or equal to 5 um. However, Kumakura discusses thickness dimension for various device layers within the above claim range (see column 5, line 5, 41-46 & column 6, lines 35-40). This claim dimension would have been obvious to one of the ordinary skill in the art in view of Kumakura. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness/distance to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use said claim dimension for a maximum value of the distance between the first sidewall surface and the second sidewall surface in a direction parallel to the first principal surface.
The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious).
Claims 5, 9 & 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kumakura as applied to claim 1 above, and further in view of OKURA (WO 2019/220788).
Regarding claim 5, Kumakura is silent on the semiconductor device as claimed in claim 1, wherein in a plan view viewed in a direction perpendicular to the first principal surface, the first opening has a rounded rectangular shape with a minimum curvature radius greater than or equal to 10 um and less than or equal to 100 um at each of four corners thereof. However, OKURA teaches wherein a first opening has a rounded rectangular shape to efficiently accommodate subsequent device components (Fig. 3-5 and associated text). Perhaps in the interest of brevity, both Kumakura and OKURA are silent on a minimum curvature radius greater than or equal to 10 um and less than or equal to 100 um at each of four corners of the first opening. However, Kumakura discusses thickness/distance dimensions within the above radius range in column 5, line 5, 41-46 & column 6, lines 35-40). These claim dimensions would have been obvious to one of the ordinary skill in the art in view of Kumakura and OKURA. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness/distance/diameter to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use said claim dimension for the radius of the first opening.
The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 9, while Kumakura teaches the semiconductor device as claimed in claim 1, wherein: the first passivation layer 31 is in contact with a side surface of the electrode 21 and covers a portion of an upper surface of the electrode 21 (see Fig. 2); however, Kumakura is silent on the first passivation layer being in contact with a side surface of the plating layer. Nonetheless, OKURA teaches wherein a first passivation layer 23 is in contact with a side surface of a plating layer 24 (Fig. 17 & Para [0056]). This has the advantages of reducing stress, suppressing cracks in the electrode and prevents peeling of the second passivation layer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Kumakura with the first passivation structure, as taught by OKURA, so as to obtain an improved semiconductor device.
Regarding claim 11, while Kumakura teaches the semiconductor device as claimed in claim 1, further comprising: an ohmic layer provided on the first principal surface of the substrate ((column 10, lines 21-23), wherein: the electrode 21 is provided on the ohmic layer, the first passivation layer 31 is in contact with a side surface of the electrode 21 and covers a portion of an upper surface of the electrode 21 (Fig. 2); however, Kamakura is silent on the first passivation layer 31 being in contact with a side surface of the plating layer. Nonetheless, OKURA teaches wherein a first passivation layer 23 is in contact with a side surface of a plating layer 24 (Fig. 17 & Para [0056]). This has the advantages of reducing stress, suppressing cracks in the electrode and prevents peeling of the second passivation layer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Kumakura with the first passivation structure, as taught by OKURA, so as to obtain an improved semiconductor device.
Regarding claim 12, the combination of Kumakura and OKURA teaches the semiconductor device as claimed in claim 11, wherein the second passivation layer 26 is in contact with the side surface of the plating layer 24 and covers a portion of an upper surface of the plating layer 24 (see OKURA’s Fig. 17).
Response to Arguments
Applicant's arguments filed 05/14/2026 have been fully considered but they are not moot in light of new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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