DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/294,233 filed on 02/01/2024 with Preliminary Amendment. Claims 1-10 are pending in the office action.
Claim 10 has been amended.
Claim 11 has been canceled.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN20110952814.5, filed on 08/19/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/02/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1: recited the limitation “testing one by one” and “obtaining a timing results of the at least one spare correction cell” that unclear the phrase “one by one” referred to which element/subject (e.g., a first normal logic cell or at least one spare correction cell) and also unclear whether “a timing result” referred to “a timing tested result” or “a timing results after correction”?
Claim 9 has similar issue as claim 1. Thus, claim 9 is also rejected as similar above.
Claims 2-8 and 10 are also rejected because are depended directly or indirectly from claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akiyama (U.S. Pub. 20150074630).
With respect to claims 1 and 9-10: Akiyama discloses a computer device, computer readable storage medium, and a method (‘630, the abstract, and claim 9) for timing correction of an integrated circuit, wherein the integrated circuit comprises a plurality of normal logic cells (‘630, fig. 2, driver and receiver) and a plurality of spare correction cells (‘630, fig. 2, S1-S10, buffers), the method for timing correction comprises:
determining a timing path with a timing error and a first normal logic cell in the timing path that does not meet a timing requirement in the integrated circuit (‘630, the abstract, paragraph [0008], detecting a path (timing path) having a constraint violation (such as timing) in a laid-out semiconductor device, also see paragraph [0010] [0017] [0018], and fig. 1, timing analysis section 3);
setting a search range around the first normal logic cell and determining at least one spare correction cell for timing correction within the search range (‘630, par. [0018] and par. [0019] and also see fig. 2-3, spare correction cells (buffers) S1-S10);
testing one by one and obtaining a timing result of the at least one spare correction cell for timing correction used in the integrated circuit (‘630, par. [0020] [0021], evaluation);
determining a target spare correction cell (i.e., set to be a candidate for the cell to be moved) for timing correction in the integrated circuit according to the timing result, wherein the target spare correction cell is at least one of the at least one spare correction cell for timing correction (‘630, par. [0023]-[0024]).
With respect to claim 2: Akiyama discloses the method for timing correction according to claim 1, wherein the method for timing correction further comprises: obtaining a cell type and physical position of the first normal logic cell (‘630, fig. 2, receiver/driver and position od receiver/driver and see par. [0018]).
With respect to claim 4: Akiyama discloses the method for timing correction according to claim 1, wherein the method for timing correction further comprises:
searching for a spare cell in the search range, and determining a target spare cell according to the spare cell (‘630, par. [0019]);
modifying a wire network connection according to the target spare cell (‘630, fig. 3, pre-movement wiring length).
With respect to claim 5: Akiyama discloses the method for timing correction according to claim 1, wherein the method for timing correction further comprises:
searching for a filler cell in the search range (‘630, par. [0019]), wherein a width of the filler cell is larger than a width of a buffer cell (‘630, par. [0022] and fig. 2-3, S4+S6 cells);
determining a target buffer cell according to the buffer cell (‘630, par. [0023] [0024]);
modifying a wire network connection according to the target buffer cell (‘630, fig. 3, pre-movement wiring length), wherein the method for timing correction further comprises back-filling at least one filler cell (‘630, fig. 2, S10 at space 41).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama (U.S. Pub. 20150074630) in view of McElvain et al., (U.S. Pub. 20040243964).
With respect to claim 3: Akiyama teaches the method for timing correction according to claim 1, wherein setting a search range around the first normal logic cell comprises:
setting a distance parameter (position in the timing path) (‘630, par. [0008], par. [0014] and fig. 3);
Akiyama does not teach determining that the search range is within a Manhattan distance of the first normal logic cell and the distance parameter.
McElvain teaches estimating a first distance between a drive element and a load element of the drive element according to a design of the circuit; verifying whether or not a timing constraint is satisfied using the first distance; estimating a second distance between the drive element and the load element according to the design of the circuit, the second distance being longer than the first distance; and determining whether or not a timing constraint is satisfied using the second distance (‘964, par. [0012]). The distance is estimated as a function of a minimum routing distance (e.g., the Manhattan distance) between the drive element and the first one of the plurality of load elements and a length of a short side of the bounding box (‘964, par. [0014]).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine McElvain and Akiyama to using McElvain’s a function of a minimum routing distance (e.g., the Manhattan distance) between the driver and receiver (load) elements to reduce the possibility of a timing problem in a subsequent routing solution, a transformation can be selectively applied to the circuit design to an extent not worsening a cost function (‘964, the abstract).
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach
claim 6: wherein setting a search range around the first normal logic cell comprises: setting a distance parameter; traversing a combined logic cell on a timing violation path; determining that the search range is within a Manhattan distance of the combined logic cell and the distance parameter.
claim 7: wherein the method for timing correction further comprises:
searching for a spare cell that is functionally consistent with the first normal logic cell in the search range, and determining a target spare cell according to the spare cell; modifying a wire network connection according to the target spare cell.
claim 8: wherein the method for timing correction further comprises:
searching for a filler cell in the search range, wherein a width of the filler cell is larger than a width of a functional cell; searching for the functional cell that is functionally consistent with the first normal logic cell; deleting an original filler cell and determining a target functional cell according to the functional cell; modifying a wire network connection according to the target functional cell, wherein the method for timing correction further comprises back-filling at least one filler cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGHIA M DOAN whose telephone number is (571)272-5973. The examiner can normally be reached Mon - Fri 7:00 AM - 5:00 PM.
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851
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