Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/06/2026 has been entered.
Response to Arguments/Amendments
Applicant's amendments to claims 1, 11 and 15 and corresponding arguments, pages 7-8 of the remarks, filed 07/06/2026, with respect to 35 U.S.C 103 rejections of the claims as unpatentable over US20210036109A1; Kim et al.; (hereinafter “Kim”) in view of US20150279925A1; Breil et al.; (hereinafter “Breil”) have been fully considered and are persuasive. Hence, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 102(a)(1) as being unpatentable over US20220302139A1; Niguchi et al.; (hereinafter “Niguchi”). Niguchi has been introduced in view of the amendments to claims 1, 11 and 15 (see 35 U.S.C. 102 rejections of claims 1, 11 and 15 below).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/22/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6 and 9-18 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Niguchi.
Regarding Claim 1 (currently amended), Niguchi teaches a semiconductor device ([0027]) comprising:
gate structures (#S2, Figure 20) comprising conductive layers (#6) extending in a first direction;
channel structures (#1-5/#H1) located in the gate structures (#S2) and protruding from surfaces of the gate structures (#1-5 extends below #S2);
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a slit structure (#H5) located between the gate structures (#S2) and comprising a protrusion (#PR, Figure 20 of Niguchi annotated) that protrudes from the surfaces of the gate structures (#S2) and comprises a protruding surface (#PS) at an end of the protrusion (#PR) and spaced apart from the gate structures (#S2) and a sidewall (#SW) between the protruding surface (#PS) and the gate structures (#S2); and
a compressive stressor (#22f, [0075], silicon oxide SiO film formed through an oxidation of a surface of source structure) connected to the protrusion (#PR) of the slit structure (#H5) and extending in the first direction, wherein the compressive stressor is spaced apart from the gate structures and is disposed on the protruding surface (#22f disposes on surface #PS spaced apart from stacked film #S2).
Regarding Claim 2, Niguchi teaches the semiconductor device as described in claim 1, wherein Niguchi further teaches the compressive stressor comprises an insulating material ([0075], oxidized film #22f comprises SiO).
Regarding Claim 4, Niguchi teaches the semiconductor device as described in claim 1, wherein Niguchi further teaches the compressive stressor comprises a dopant ([0073-0075], #22f is formed through an oxidation of a surface of P-doped polysilicon layer #22d).
Regarding Claim 5, Niguchi teaches the semiconductor device as described in claim 1, wherein Niguchi further teaches the compressive stressor comprises boron (B), phosphorus (P), or arsenic (As), or a combination thereof ([0073-0075], #22f is formed through an oxidation of a surface of P-doped polysilicon layer #22d).
Regarding Claim 6, Niguchi teaches the semiconductor device as described in claim 1, wherein Niguchi further teaches the gate structures are adjacent to each other in a second direction that is perpendicular to the first direction (Figure 20, stacked film #S2 extend vertically and are adjacent to each other horizontally).
Regarding Claim 9, Niguchi teaches the semiconductor device as described in claim 1, wherein Niguchi further teaches comprising:
a source structure (#22, Figure 20, source lines),
wherein the protrusion of the slit structure (#PR, Figure 20 of Niguchi annotated) and the compressive stressor (#22f) are located inside the source structure (#22).
Regarding Claim 10, Niguchi teaches the semiconductor device as described in claim 1, wherein Niguchi further teaches the slit structure (#H5, Figure 20) comprises an insulating layer (#29, insulating film).
Regarding Claim 11 (currently amended), Niguchi teaches a semiconductor device ([0027]) comprising:
a source structure (#22, Figure 20) disposed over a substrate (#11);
gate structures (#S2) disposed over the substrate (#11), comprising gate lines (#6) extending in a first direction, and located adjacent to each other in a second direction other than the first direction (electrode layers #6 are adjacent each other in horizontal/vertical direction);
a slit structure (#H5) located between the gate structures (#S2) and protruding into the source structure along a third direction other than the first direction and the second direction (slit #H5 protrudes into source lines #22), and including a protruding surface (#PS, Figure 20 of Niguchi annotated) at an end of the slit structure (#H5) disposed within the source structure (#22) and spaced apart from the gate structures (#S2); and
an oxidized pattern (#22f, [0075], silicon oxide film formed through an oxidation of a surface of source structure) disposed on the protruding surface (#PS) and extending in the first direction inside the source structure and pressing the substrate in the third direction (oxidized film #22f extends into source lines #22 pressing substrate #11).
Regarding Claim 12, Niguchi teaches the semiconductor device as described in claim 11, wherein Niguchi further teaches the oxidized pattern (#22f, Figure 20) is connected to the slit structure (#H5).
Regarding Claim 13, Niguchi teaches the semiconductor device as described in claim 11, wherein Niguchi further teaches the oxidized pattern comprises a dopant ([0073-0075], #22f is formed through an oxidation of a surface of P-doped polysilicon layer #22d).
Regarding Claim 14, Niguchi teaches the semiconductor device as described in claim 11, wherein Niguchi further teaches the oxidized pattern comprises boron (B), phosphorus (P), or arsenic (As), or a combination thereof ([0073-0075], #22f is formed through an oxidation of a surface of P-doped polysilicon layer #22d).
Regarding Claim 15 (currently amended), Niguchi teaches a semiconductor device ([0027]) comprising:
gate structures (#S2, Figure 20) each including conductive layers alternately stacked with insulating layers (alternate electrode layers #11 and insulating layers #14);
a source structure (#22) disposed over the gate structures (#S2);
channel structures (#1-5/#H1) extending through the gate structures (#S2) and connected to the source structure (#22);
an insulating slit structure (#H5, [0078]) disposed between the gate structures (#S2) and protruding into the source structure (#22); and
a compressive stressor (#22f, [0075], silicon oxide film formed through an oxidation of a surface of source structure) disposed within the source structure (#22) on an end of the insulating slit structure (#22f disposes on one end of slit #H5), wherein the compressive stressor (#22f) is spaced apart from the gate structures (#S2).
Regarding Claim 16, Niguchi teaches the semiconductor device as described in claim 11, wherein Niguchi further teaches the protruding surface (#PS, Figure 20 of Niguchi annotated) is parallel to a surface of the source structure (#22).
Regarding Claim 17, Niguchi teaches the semiconductor device as described in claim 15, wherein Niguchi further teaches the insulating slit structure (#H5, Figure 20 of Niguchi annotated) includes an upper surface (#PS) at the end of the insulating slit structure and a sidewall (#SW) between the upper surface (#PS) and the gate structures (#S2); and
wherein the compressive stressor (#22f) is disposed on the upper surface (#PS).
Regarding Claim 18, Niguchi teaches the semiconductor device as described in claim 17, wherein Niguchi further teaches the upper surface (#PS, Figure 20 of Niguchi annotated) is parallel to an upper surface of the source structure (#22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Niguchi in view of Kim.
Regarding Claim 8, Niguchi teaches the semiconductor device as described in claim 1, wherein Niguchi further teaches the slit structure (#H5, Figure 20) comprises:
an insulating spacer (#27a) surrounding a sidewall of the slit structure (#H5).
Niguchi does not explicitly teach the slit structure comprises a source contact plug.
However, Kim teaches a semiconductor device (Figure 1), comprising a slit structure (#SL, slit) comprises a source contact plug (#17/17A, source contact structure).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Niguchi with the teaching of Kim in order to provide contact to the source structure in comparable devices according to Kim, [0025].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20220238684A1 – Figure 1A, [0035]
US20180374868A1 – Figures 1-3, 19, 24
US20190019808A1 – Figure 1, [0126]
US20230209831A1 – Figures 1A, 3D, [0076]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIEN TRAN whose telephone number is (571)272-6967. The examiner can normally be reached Monday-Thursday 9:00 am - 6:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE S KIM can be reached on (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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