Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments/Amendments
Applicant's amendments to claims 1 and 11 and corresponding arguments, pages 9-11 of the remarks, filed 02/06/2026, with respect to 35 U.S.C 102(a)(1) rejections of claims 1 and 11 as unpatentable over US11296188B2 (or US20210036109A1); Kim et al.; (hereinafter “Kim”) have been fully considered and are persuasive. Hence, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Kim in view of US20150279925A1; Breil et al.; (hereinafter “Breil”). Breil has been introduced in view of the amendments to claims 1 and 11 (see 35 U.S.C. 103 rejection of claims 1 and 11 below).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 and 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Breil.
Regarding Claim 1 (currently amended), Kim teaches a semiconductor device (col. 1, ln. 42-49) comprising:
gate structures (#ST, Figure 1) comprising conductive layers extending in a first direction (#11, conductive layers, wherein #ST extends vertically);
channel structures (#CH) located in the gate structures (#ST) and protruding from surfaces of the gate structures (Figure 1, #CH extends vertically pass bottom insulating layer #12);
a slit structure located between the gate structures (col. 9, ln. 16-22, slit #SL passes through #ST) and comprising a protrusion that protrudes from the surfaces of the gate structures (Figure 1, #SL extends vertically pass bottom insulating layer #12); and
a compressive stressor (#21, col. 5, ln. 5-11, protective pattern formed by selective oxidation) connected to the protrusion of the slit structure and extending in the first direction (#21 extends at least vertically connecting to bottom end of #SL).
Kim does not explicitly teach the compressive stressor is spaced apart from the gate structures.
However, Breil teaches a semiconductor device ([0013]), comprising a compressive stressor (#340, Figure 9, [0025], compressive stress layer) spaced apart from gate structure (#340 disposes only within polysilicon substrate #302).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kim with the teaching of Breil, as it was merely a simple substitution of one known element (slit structure with protective pattern of Kim) for another (deep trench structure with compressive stress layer of Breil) to obtain predictable result. See MPEP 2143(I)(B).
Regarding Claim 2, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches the compressive stressor comprises an insulating material (Figure 1, col. 4, ln. 14-15, #21 comprises insulating material).
Regarding Claim 3, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches the protrusion of the slit structure (#SL) comprises a protruding surface (Figure 2A of Kim annotated) and a sidewall (#SW), and wherein the compressive stressor selectively surrounds the protruding surface (#21/#21A surrounds protrusion of #SL).
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Regarding Claim 4, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches the compressive stressor comprises a dopant (col. 5, ln. 1-10, #21 is formed by selective oxidation affected by dopant).
Regarding Claim 5, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches the compressive stressor comprises boron (B), phosphorus (P), or arsenic (As), or a combination thereof (col.5, ln. 11-13, dopant of #21 can be P, As or B).
Regarding Claim 6, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches the gate structures are adjacent to each other in a second direction that is perpendicular to the first direction (Figure 1, stacks #ST extend vertically and are adjacent to each other horizontally).
Regarding Claim 8, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches the slit structure (#SL, Figure 1) comprises:
a source contact plug (#17, source contact); and
an insulating spacer (#20, spacer) surrounding a sidewall of the source contact plug (Figure 1, #20 surrounds sidewalls of #17).
Regarding Claim 9, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches comprising:
a source structure (#13, Figure 1, source structure),
wherein the protrusion of the slit structure (Figure 2A of Kim annotated) and the compressive stressor (#21) are located inside the source structure (protruding surface and #21 dispose inside #13).
Regarding Claim 10, Kim in view of Breil teaches the semiconductor device as described in claim 1, wherein Kim further teaches the slit structure comprises an insulating layer (Figure 1, col. 4, ln. 2-3, #SL comprises insulating spacer #20).
Regarding Claim 11 (currently amended), Kim teaches a semiconductor device (col. 1, ln. 42-49) comprising:
a source structure (#13, Figure 1) located on a substrate (#10);
gate structures (#ST) located on the substrate (#10), comprising gate lines (#11) extending in a first direction (#11 extends horizontally/vertically), and located adjacent to each other in a second direction other than the first direction (#11 are adjacent each other in horizontal/vertical direction);
a slit structure (col. 9, ln. 16-22, slit #SL passes through #ST) located between the gate structures (#ST) and protruding into the source structure along a third direction other than the first direction and the second direction (#SL protrudes into #13 extending horizontally/vertically/out of the page); and
an oxidized pattern (#21, col. 5, ln. 5-11, protective pattern formed by selective oxidation) extending in the first direction inside the source structure and pressing the substrate in the third direction (#21 extends horizontally/vertically/out of the page inside #13 pressing base #10).
Kim does not explicitly teach the oxidized pattern is spaced apart from the gate structures.
However, Breil teaches a semiconductor device ([0013]), comprising an oxidized pattern (#340, Figure 9, [0025-0026], compressive stress layer) spaced apart from gate structure (#340 disposes only within polysilicon substrate #302).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kim with the teaching of Breil, as it was merely a simple substitution of one known element (slit structure with oxidized pattern of Kim) for another (deep trench structure with compressive stress layer of Breil) to obtain predictable result. See MPEP 2143(I)(B).
Regarding Claim 12, Kim teaches the semiconductor device as described in claim 1, wherein Kim further teaches the oxidized pattern (#21, Figure 1) is connected to the slit structure (#21 surrounds bottom portion of slit #SL).
Regarding Claim 13, Kim teaches the semiconductor device as described in claim 1, wherein Kim further teaches the oxidized pattern comprises a dopant (col. 5, ln. 1-10, #21 is formed by selective oxidation affected by dopant).
Regarding Claim 14, Kim teaches the semiconductor device as described in claim 1, wherein Kim further teaches the oxidized pattern comprises boron (B), phosphorus (P), or arsenic (As), or a combination thereof (col.5, ln. 11-13, dopant of #21 can be P, As or B).
Regarding Claim 15, Kim teaches a semiconductor device (col. 1, ln. 42-49) comprising:
gate structures (#ST, Figure 1) each including conductive layers alternately stacked with insulating layers (alternate conductive layers #11 and insulating layers #12);
a source structure (#13) disposed over the gate structures (#ST);
channel structures (#CH) extending through the gate structures (#ST) and connected to the source structure (#13);
an insulating slit structure (col. 9, ln. 16-22, slit #SL) disposed between the gate structures (#ST) and protruding into the source structure (#13); and
a compressive stressor (#21, col. 5, ln. 5-11, protective pattern formed by selective oxidation) disposed in the source structure (#13) and contacting the insulating slit structure (#21 contacts one end of slit structure #SL).
Kim does not explicitly teach the compressive stressor is spaced apart from the gate structures.
However, Breil teaches a semiconductor device ([0013]), comprising a compressive stressor (#340, Figure 9, [0025], compressive stress layer) spaced apart from gate structure (#340 disposes only within polysilicon substrate #302).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kim with the teaching of Breil, as it was merely a simple substitution of one known element (slit structure with protective pattern of Kim) for another (deep trench structure with compressive stress layer of Breil) to obtain predictable result. See MPEP 2143(I)(B).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIEN TRAN whose telephone number is (571)272-6967. The examiner can normally be reached Monday-Thursday 9:00 am - 6:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE S KIM can be reached on (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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