Attorney Docket Number: 138877-5124-US
Filing Date: 04/04/2023
Claimed Priority Date: 08/18/2022 (KR 10-2022-0103154)
Inventors: Kim et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 02/12/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 02/12/2026 in reply to the previous Office action mailed on 02/12/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20, with claims 3, 13, and 20 remaining withdrawn from consideration.
Initial Remarks
For all instances of “Annotated Fig. 2”, please refer to the following image presented below. “Annotated Fig. 2” is a magnified version of Figure 2 of Choi (US 2021/0272930) with markings denoting specific features, drawn for clarity purposes. No other changes have been made to the figure.
PNG
media_image1.png
585
1000
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7, 9-12, 15-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0272930) in view of Kim (US 2021/0280540).
Regarding claims 11 and 1, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows most aspects of the instant invention, including a semiconductor package 1000 comprising:
a package substrate 100;
an interposer 300 disposed on the package substrate (see, e.g., par.0031/ll.1-2);
a logic semiconductor device (rightmost 400) (see, e.g., par.0045/ll.14-17) disposed on the interposer; and
a memory semiconductor device disposed on the interposer to be spaced apart from the logic semiconductor device, wherein the memory semiconductor device further includes, a memory chip (leftmost 400) (see, e.g., par.0045/ll.9-10) having a plurality of chip pads (four leftmost 420) disposed on a first surface 400S of the memory chip;
a redistribution layer 310/320 disposed on the first surface of the memory chip, wherein:
the redistribution layer is electrically connected to the plurality of chip pads (four leftmost 420) (see, e.g., par.0031/ll.21-24);
the redistribution layer has a plurality of first redistribution pads (314 in “First Region”) disposed on a first surface 300S1 of the redistribution layer in a first region (“First Region”) of the redistribution layer; and
the redistribution layer has a plurality of second redistribution pads (314 in “Second Region”) disposed on the first surface of the redistribution layer in a second region (“Second Region”) of the redistribution layer;
a processor chip (leftmost 200) (see, e.g., par.0033/ll.15-17) disposed on the first region (“First Region”) of the redistribution layer and electrically connected to the plurality of first redistribution pads (314 in “First Region”) (see, e.g., par.0038/ll.1-4);
a sealing member 290 disposed on the first surface 300S1 of the redistribution layer and covering the processor chip; and
a plurality of conductive structures 280 disposed on the second region (“Second Region”) of the redistribution layer, the plurality of conductive structures penetrating through the sealing member and extending upwardly in a vertical direction away from the plurality of second redistribution pads (314 in “Second Region”)
Regarding claims 11 and 1, Choi shows most aspects of the invention. However, the embodiment in figure 2 does not explicitly disclose that the redistribution layer is directly disposed on the plurality of chip pads, as recited in claims 11 and 1, and that an outer side surface of the memory chip and an outer side surface of the redistribution layer are coplanar with each other, as recited in claim 1. Choi nevertheless teaches such features in alternative embodiments. Specifically, Choi discloses that Choi’s redistribution layer 310/320 may be directly disposed on Choi’s plurality of chip pads (four leftmost 420) by directly bonding the chip pads of the memory chip with pads of the redistribution layer, resulting in an outer side surface of the memory chip 400S and an outer side surface 300S2 of the redistribution layer being coplanar with each other (see, e.g., fig. 12 and par.0083/ll.9-15). Kim, in the same field of endeavor and in a similar device to Choi, teaches that such direct bonding practices reduce the form factor of semiconductor packages, thereby improving the performances of incorporated components or devices in and/or coupled to the semiconductor package (see, e.g., Kim: pars.0024 and 0032/ll.15-21).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the primary embodiment of Choi to include the redistribution layer directly disposed on the plurality of chip pads, as recited in claims 11 and 1, such that an outer side surface of the memory chip and an outer side surface of the redistribution layer are coplanar with each other, as recited in claim 1, as taught in these alternative embodiments. Doing so would have been motivated by the fact that Choi validates such features as compatible and integrable with Choi’s invention and the express teachings of Kim to (1) promote miniaturization and scalability, by reducing the form factor of the overall semiconductor package, and (2) improve electrical capacity, operability, and functionality, by improving the performances of incorporated components or devices in and/or coupled to the semiconductor package.
Regarding claims 12 and 2, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows that the processor chip (leftmost 200) includes:
a plurality of second chip pads (three leftmost 220) disposed on a first surface 200S of the processor chip facing the first surface 300S1 of the redistribution layer 310/320; and
a plurality of solder bumps (three leftmost 240) (see, e.g., par.0035/ll.12-13) respectively disposed on the plurality of second chip pads and respectively bonded to the plurality of first redistribution pads (314 in “First Region”) (see, e.g., par.0035/ll.9-11)
Regarding claims 15 and 5, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows wherein that:
each of the plurality of conductive structures 280 has a first height from the first surface of the redistribution layer 300S1 to a distal end of each of the plurality of conductive structures; and
an upper surface 200SO of the processor chip has a second height less than or equal to the first height from the first surface of the redistribution layer
Regarding claims 17 and 7, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows that the plurality of conductive structures 280 are/is arranged in the sealing member 290 to be outside the processor chip.
Regarding claim 6, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows a plurality of conductive bumps 260 respectively disposed at a distal end of the plurality of conductive structures 280 exposed from the sealing member 290.
Regarding claim 9, Choi (see, e.g., par.0037/ll.13) shows that the plurality of conductive structures 280 includes copper (Cu).
Regarding claim 10, Choi (see, e.g., pars.0033/ll.15-17 and 0045/ll.18-21) shows that the processor chip (leftmost 200) includes Application Processor (AP) and the memory chip (leftmost 400) includes DRAM.
Regarding claim 16, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows that the memory semiconductor device further includes a plurality of conductive bumps 260 respectively disposed at a distal end of the plurality of conductive structures 280 exposed from the sealing member 290.
Regarding claim 19, Choi (see, e.g., pars.0033/ll.15-17 and 0045/ll.12-21) shows that each of the logic semiconductor device (rightmost 400) and the processor chip (leftmost 200) includes Application Processor (AP) and the memory chip (leftmost 400) includes DRAM.
Claims 14 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Choi/Kim in view of Sankman (US 2020/0006293).
Regarding claims 14 and 4, Choi/Kim shows most aspects of the invention (see paragraphs 7-8 above). Furthermore, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows that each of the plurality of conductive structures has a height and a diameter. Choi additionally teaches that various changes and structural modifications may be made to Choi’s device without departing from the scope of Choi’s invention (see, e.g., par.0127). Choi, however, fails to specify that a height of each of the plurality of conductive structures is in a range of 100 µm to 400 µm and that a diameter of each of the plurality of conductive structures is in a range of 100 µm to 400 µm. Sankman, in the same field of endeavor and in a similar device to Choi, teaches that the heights and diameters of each of a plurality of conductive structures 112 can comprise a multitude of ranges, and further teaches an example wherein a height of each of the plurality of conductive structures is in a range of 100 µm to 400 µm and a diameter of each of the plurality of conductive structures is in a range of 100 µm to 400 µm (see, e.g., Sankman: fig. 1A and par.0029/ll.14-19). Sankman teaches that the physical parameters of conductive structures may be selected according to desired design specifications of a semiconductor package (see, e.g., Sankman: par.0029/ll.8-10).
Sankman is evidence showing that one of ordinary skill in the art would appreciate that having a height and a diameter of each of a plurality of conductive structures be, respectively, in a range of 100 µm to 400 µm would be equivalent to having a height and a diameter of each of a plurality of conductive structures be within any other range, and that such differences would result in no unexpected changes in the performance of the device of Choi. That is, the conductive structure heights and diameters of both Sankman and Choi would yield the predictable result of providing a suitable conductive pathway connecting a chip and a package substrate.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a height of each of the plurality of conductive structures be in a range of 100 µm to 400 µm and a diameter of each of the plurality of conductive structures be in a range of 100 µm to 400 µm, as taught by Sankman, or to have the respective heights and diameters of a plurality of conductive structures be within any other range, because these were recognized as equivalents in the semiconductor art and because such parameters may be adjusted based on the desired design characteristics of a semiconductor package, as taught by Sankman, of which modifications would be within the level of ordinary skill in the art. Furthermore, both designs would yield the predictable result of providing a suitable conductive pathway connecting a chip and a package substrate. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
It is noted that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Moreover, Choi’s express teaching that a variety of structural modifications may be made to Choi’s device without departing from the scope of Choi’s invention taken together with Sankman’s disclosure the physical parameters of conductive structures may be selected according to desired design specifications of a semiconductor package would have suggested to one of ordinary skill in the art that the height and diameter dimensions of conductive structures could be adjusted to the values of the claimed dimensions (100 µm to 400 µm) as a matter of routine optimization of a result-effective variable. Adjusting height to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, would have been well within the ordinary skill in the art. No evidence of criticality of unexpected results for the claimed dimensions is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Nevertheless, differences in height and diameter will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed height and diameter range, i.e., 100 µm to 400 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Choi.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed heights and diameters or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 18 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Choi/Kim in view of Ryu (US 2021/0013144).
Regarding claims 18 and 8, Choi/Kim shows most aspects of the invention (see paragraphs 7-8 above). Furthermore, Choi (see, e.g., fig. 2 and Annotated Fig. 2) shows that each of the plurality of first and second redistribution pads has a width. Choi additionally teaches that various changes and structural modifications may be made to Choi’s device without departing from the scope of Choi’s invention (see, e.g., par.0127). Choi, however, fails to specify that a width of each of the plurality of first and second redistribution pads is in a range of 100 µm to 500 µm. Ryu, in the same field of endeavor and in a similar device to Choi, teaches redistribution pads 119 in a semiconductor package 100, wherein Ryu further teaches that a width of each of the plurality of redistribution pads may be selected and may be in a range of 100 µm to 500 µm (see, e.g., par.0053/ll.18-19).
Ryu is evidence showing that one of ordinary skill in the art would appreciate that having a width of each of a plurality of first and second redistribution pads be in a range of 100 µm to 500 µm would be equivalent to having a width of each of a plurality of first and second redistribution pads comprise any other range, and that such differences would result in no unexpected changes in the performance of the device of Choi. That is, the redistribution pad widths of both Ryu and Choi would yield the predictable result of providing a suitable connecting bonding structure between a redistribution layer and an electronic device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a width of each of the plurality of first and second redistribution pads be in a range of 100 µm to 500 µm, as taught by Ryu, or to have the widths of the plurality of first and second redistribution be within any other range, because these were recognized as equivalents in the semiconductor art and because such parameters may be adjusted based on the desired design characteristics of a semiconductor package, of which modifications would be within the level of ordinary skill in the art. Furthermore, both designs would yield the predictable result of providing a suitable connecting bonding structure between a redistribution layer and an electronic device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
It is noted that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Moreover, Choi’s express teaching that a variety of structural modifications may be made to Choi’s device without departing from the scope of Choi’s invention taken together with Ryu’s disclosure that the physical parameters of redistribution pads may be selected according to desired design specifications would have suggested to one of ordinary skill in the art that the width dimensions of redistribution pads could be adjusted to the values of the claimed dimensions (100 µm to 500 µm) as a matter of routine optimization of a result-effective variable. Adjusting width to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, would have been well within the ordinary skill in the art. No evidence of criticality of unexpected results for the claimed dimensions is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Nevertheless, differences in width will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality (see next paragraph below) of the claimed widths, i.e., 100 µm to 500 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Choi. See also the comments stated above in paragraphs 18-26 with respect to claims 14 and 4 regarding criticality, which are considered to be repeated here.
Response to Arguments
Applicant’s amendments to the specification have overcome the objections to the drawings put forth in the previous Office action mailed on 11/12/2025. Accordingly, the objections to the drawings put forth in the previous Office action are hereby withdrawn.
Applicant’s amendments to the claims have overcome the claim objections put forth in the previous Office action mailed on 11/12/2025. Accordingly, the claim objections put forth in the previous Office action are hereby withdrawn.
Applicant’s amendments to the claims have overcome the 35 U.S.C. 112 rejections put forth in the previous Office action mailed on 11/12/2025. Accordingly, the 35 U.S.C. 112 rejections put forth in the previous Office action are hereby withdrawn.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights