DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/4/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 11/12/2025 is acknowledged.
Claims 15-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/12/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the upper surface side” in line 4 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation “the bottom surface side” in line 5 of the claim. There is insufficient antecedent basis for this limitation in the claim.
A. Prior-art rejections based at least in part by Yamamoto
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto et al. (US 2018/0108618 A1, hereinafter “Yamamoto”).
Regarding independent claim 1, Figure 1 of Yamamoto discloses an electronic circuit package comprising:
a package board 2 (“wiring board”- ¶0029) having an upper surface, a bottom surface positioned on a side opposite to the upper surface, and a side surface connecting the upper and bottom surfaces;
an electronic component 3 (“components”- ¶0029) mounted on the upper surface of the package board 2;
a first protective layer 4/8 (collectively 4 “resin layer” and 8 “adhesion layer”-¶¶0029, 0034), covering the upper surface of the package board 2 so as to embed therein the electronic component 3; and
a second protective layer 9 (“conductive layer”- ¶0034) covering the side surface of the package board 2,
wherein the first and second protective layers 4/8, 9 contacting each other.
Regarding claim 2, Figure 1 of Yamamoto discloses wherein the second protective layer 4/8 (which comprises Cr- ¶0035) is made of a different material from the first protective layer 9 (which comprises Cu or Al- ¶0036) (¶¶0033, 0035-0036).
Regarding claim 3, Figure 1 of Yamamoto discloses wherein the second protective layer 9 is lower in hardness than the first protective layer 4/8, since layer 9 can be comprised of copper (Cu) or aluminum (Al), which has a lower Vickers hardness1 than chromium (Cr) (see Fig. 2), which is part of layer 8 (¶¶0035-0036).
Regarding claim 8, Figure 1 of Yamamoto discloses the first protective layer 4/8 further covers a part of the side surface of the package board 2.
B. Prior-art rejections based at least in part by Uezato
Claim Rejections - 35 USC § 102
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Uezato et al. (US 2023/0282601 A1, hereinafter “Uezato”).
Regarding independent claim 1, Figure 2 of Uezato discloses an electronic circuit package comprising:
a package board 13 (“plate”- ¶0033) having an upper surface, a bottom surface positioned on a side opposite to the upper surface, and a side surface connecting the upper and bottom surfaces;
an electronic component 11 (“semiconductor element”- ¶0033) mounted on the upper surface of the package board 13;
a first protective layer 18 (“sealing material”- ¶0033) covering the upper surface of the package board 13 so as to embed therein the electronic component 11; and
a second protective layer 16 (“case”- ¶0033) covering the side surface of the package board 13,
wherein the first and second protective layers 18, 16 contacting each other.
Regarding claim 5, Figure 2 of Uezato discloses wherein the second protective layer 16 further covers a part of the upper surface of the package board 13 without covering the electronic component 11.
C. Prior-art rejections based at least in part by Kang
Claim Rejections - 35 USC § 102
Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2020/0194380 A1, hereinafter “Kang”).
Regarding independent claim 1, Figure 4A of Kang discloses an electronic circuit package comprising:
a package board 100 (“substrate”- ¶0024) having an upper surface, a bottom surface positioned on a side opposite to the upper surface, and a side surface connecting the upper and bottom surfaces;
an electronic component 200 (“chip”- ¶0024) mounted on the upper surface of the package board 100;
a first protective layer 300 (“molding layer”- ¶0024) covering the upper surface of the package board 100 so as to embed therein the electronic component 200; and
a second protective layer 400 (“shield layer”- ¶0024) covering the side surface of the package board 100,
wherein the first and second protective layers 300, 400 contacting each other.
Regarding claim 9, Figure 4A of Kang discloses the electronic circuit package further comprising a plurality of terminal electrodes 130G, 130S (“terminals”- ¶0024) provided on the bottom surface of the package board 100.
Regarding claim 10, Figure 4A of Kang discloses wherein the second protective layer 400 further covers a part of the bottom surface of the package board 100 without covering the terminal electrodes 130G, 130S.
D. Prior-art rejections based at least in part by Bonnici
Claim Rejections - 35 USC § 102
Claims 1 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bonnici et al. (US 2019/0157176 A1, hereinafter “Bonnici”).
Regarding independent claim 1, Figures 1A-1D of Bonnici disclose an electronic circuit package comprising:
a package board 106 (“substrate- ¶0014) having an upper surface, a bottom surface positioned on a side opposite to the upper surface, and a side surface (collectively the upper and lower side surfaces of 106) connecting the upper and bottom surfaces;
an electronic component 102 (“die”- ¶0014) mounted on the upper surface of the package board 106;
a first protective layer 114 (“encapsulation material”- ¶0019) covering the upper surface of the package board 106 so as to embed therein the electronic component 102; and
a second protective layer 116 covering the side surface of the package board,
wherein the first and second protective layers 114, 116 contacting each other.
Regarding claim 13, Figures 1A-1D of Bonnici disclose wherein the side surface of the package board 106 includes an upper area (i.e., the upper side surface of 106) positioned on the upper surface side and a lower area (i.e., the lower side surface of 106) positioned on the bottom surface side, and wherein a part of the lower area is exposed without being covered with the second protective layer 116.
Regarding independent claim 14, Figures 1A-1D of Bonnici disclose an electronic device comprising:
a circuit board (i.e., “PCB”- ¶0017); and
an electronic circuit package 100 (“package”- ¶0013) mounted on the circuit board (¶0017), wherein the electronic circuit package 100 comprising:
a package board 106 (“substrate- ¶0014) having an upper surface, a bottom surface positioned on a side opposite to the upper surface, and a side surface (collectively the upper and lower side surfaces of 106) connecting the upper and bottom surfaces;
an electronic component 102 (“die”- ¶0014) mounted on the upper surface of the package board 106;
a first protective layer 114 (“encapsulation material”- ¶0019) covering the upper surface of the package board 106 so as to embed therein the electronic component 102; and
a second protective layer 116 covering the side surface of the package board, and
wherein the first and second protective layers 114, 116 contacting each other.
Allowable Subject Matter
Claims 4, 6-7 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art of record including Yamamoto, Uezato, Kang and/or Bonnici, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the first and second protective layers are made of an epoxy-based resin material”.
Regarding claim 6, the prior art of record including Yamamoto, Uezato, Kang and/or Bonnici, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the package board has an edge positioned at a boundary between the upper and side surfaces, and wherein the edge has a first portion covered with the second protective layer and a second portion not covered with the second protective layer”.
Regarding claim 7, the prior art of record including Yamamoto, Uezato, Kang and/or Bonnici, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the side surface of the package board includes first and second side surfaces opposite to each other and third and fourth side surfaces perpendicular to the first and second side surfaces and opposite to each other, wherein the package board has first to fourth edges positioned respectively at boundaries between the upper surface and the first to fourth side surfaces, and wherein the second protective layer further covers a part of the upper surface of the package board beyond the first to fourth edges”.
Regarding claim 11, the prior art of record including Yamamoto, Uezato, Kang and/or Bonnici, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the package board has an edge positioned at a boundary between the bottom surface and the side surface, and wherein the edge has a first portion covered with the second protective layer and a second portion not covered with the second protective layer”.
Regarding claim 12, the prior art of record including Yamamoto, Uezato, Kang and/or Bonnici, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the side surface of the package board includes first and second side surfaces opposite to each other and third and fourth side surfaces perpendicular to the first and second side surfaces and opposite to each other, wherein the package board has first to fourth edges positioned respectively at boundaries between the bottom surface and the first to fourth side surfaces, and wherein the second protective layer further covers a part of the bottom surface of the package board beyond the first to fourth edges”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chang et al. (US 2013/0320572 A1), which discloses an electronic circuit package comprising first and second protective layers covering a package board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
1 See NPL reference “U” as noted in PTO-892