Prosecution Insights
Last updated: April 19, 2026
Application No. 18/295,493

LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT

Final Rejection §102
Filed
Apr 04, 2023
Examiner
TRAN, VINCENT HUY
Art Unit
2115
Tech Center
2100 — Computer Architecture & Software
Assignee
Nvidia Corporation
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
2y 9m
To Grant
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
938 granted / 1083 resolved
+31.6% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
1122
Total Applications
across all art units

Statute-Specific Performance

§101
8.0%
-32.0% vs TC avg
§103
42.5%
+2.5% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
12.7%
-27.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1083 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 21 are pending in the application. Claims 1-13, 15-21 are allowed Examiner’s Note: The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." Response to Arguments Applicant's arguments filed 01/06/2026 have been fully considered but they are not persuasive. Applicant’s attorney argues that Yamasaki do not expressly describe each and every element of claim 14. As pointed out by the applicant, the Office Action equates Yamasaki's monitoring clock (c) with the claimed clock signal being monitored. To be equivalent to the claimed clock signal being monitored, Yamasaki would have to generate pulse trains for respective phases of Yamasaki's monitoring clock (c). Further, for Yamasaki's monitoring clock (c) to be equivalent to the claimed clock signal being monitored, this would mean that Yamasaki would have to count a number of pulses is each separate phase of Yamasaki's monitoring clock (c) indicating a duration of each of the separate phases of Yamasaki's monitoring clock (c). There is no teaching or suggestion in Yamasaki of counting pulses in each of separate phases of its monitoring clock (c). In other words, the applicant argues that the Office improperly equates Yamasaki’s monitoring clock (c) with the claimed “clock signal being monitor,” and contends that Yamasaki fails to discloses generating pulse trains corresponding to respective phases of the monitoring clock (c) or counting pulses within each phases of that monitoring clock. Note: the claims and only the claims form the metes and bounds of the invention. "Office personnel are to give the claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Limitations appearing in the specification but not recited in the claim are not read into the claim. In re Prater, 415 F.2d, 1393, 1404-05, 162 USPQ 541,550-551 (CCPA 1969)" (MPEP page 2100-8, col 2 lines 45-48; page 2100-9, col 1, lines 1-4). The Examiner has full latitude to interpret each claim in the broadest reasonable sense. Here, the rejection does not reply on measuring the phase duration of Yamasaki’s monitoring clock (c). Rather, the rejection maps: Yamasaki’s target clock to the claimed “clock signal being monitored,” Yamasaki’s monitoring clock pulses to the claimed “train of pulses corresponding to a duration of respective phases of the clock signal.” Yamasaki discloses a configuration in which monitoring clock pulses are counted while the target clock is at a high level or a low level. The counted pulses occur during the duration of each respective phase of the target clock. Thus, the number of monitoring clock pulses accumulated during each high or low phase directly corresponding to – and is indicative of – the duration of that phase. The claim does not require that the pulses be generated by the monitoring clock itself. It only requires “generating a train of pulses correspond to a duration of respective phases of the clock signal.” Yamasaki satisfied this limitation because the monitoring clock produces pulses that exist during each phase of the monitored (target) clock, and those pulses are counted to determine the duration of each phases. The pulses therefore correspond to the duration of the respective phases of the monitored clock. Further, Yamasaki discloses determining whether the counted values increase or decrease beyond expected ranges, thereby detecting when the duration of subsequent phases lengthens or shortens. Upon such determination, an abnormality signal is generated. This corresponds to the claimed determination of phases lengthening or shortening and provision of a clock abnormality detect (CAD) signal. Applicant’s argument seems to misunderstand the role of the monitoring clock (c) in Yamasaki. Yamasaki does not equate the monitoring clock (c) with “the claimed clock signal being monitored.” Instead, the “target clock” is the signal being monitored for anomalies. Yamasaki’s monitoring clock (c) is utilized to measure the duration of the phases (H and L levels) of the divided target clock. Yamasaki explicitly states, “the time width is determined based on count value obtained by counting the number of monitoring clock in the H level and L level. This means that the monitoring clock (c) acts as the unit of measurement for the phases of the target clock, not that its own phases are being measured. Therefore, the argument that Yamasaki would need to “generate pulse trains for respective phases of Yamasaki’s monitoring clock (c) and “count a number of pulses in each separate phase of Yamasaki’s monitoring clock (c) is not relevant to how Yamasaki operates. Yamasaki clearly describes counting the pulses of the monitoring clock (c) within the H and L levels of the divided target clock to determine their durations, which aligns with the “generating a train of pulses corresponding to a duration of respective phases of the clock signal” and “counting a number of pulses in respective generated pulses trains” elements of claim 14. Accordingly, the rejection is maintained. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamasaki U.S. Patent 7,391,240. Regarding claim 14, Yamasaki teaches a method of operating a clock monitoring circuit for monitoring a clock signal, comprising: generating a train of pulses corresponding to a duration of respective phases of the clock signal [SEE (c) of fig. 5 – monitoring clock; col. 3 lines 45-60, col. 5 lines 15-18]1; counting a number of pulses in respective generated pulse trains, wherein the number of pulses in each respective pulse train is indicative of the duration of the respective phases of the clock signal [SEE fig. 7-10, and 13, col. 4 lines 1-12, col. 6 lines 31-34]; determining, using the number of pulses, when durations of subsequent phases of the clock signal lengthen [SEE fig. 8]; determining, using the number of pulses, when durations of the subsequent phases of the clock signal shorten [SEE fig. 9]; and providing a clock abnormality detect (CAD) signal when the clock signal either lengthens or shortens [col. 4 lines 12-18; col. 7 line 64 to col. 8 line 12]. Allowable Subject Matter Claims 1-13, 15-21 are allowed. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT HUY TRAN whose telephone number is (571)272-7210. The examiner can normally be reached M-F 7:00-4:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini S Shah can be reached at 571-272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. VINCENT H TRAN Primary Examiner Art Unit 2115 /VINCENT H TRAN/Primary Examiner, Art Unit 2115 1 The monitoring clock generates pulses, and the counting of these pulses within the H and L levels of the target clock effectively creates a “train of pulses” whose count represents the duration of these phases.
Read full office action

Prosecution Timeline

Apr 04, 2023
Application Filed
Oct 02, 2025
Non-Final Rejection — §102
Jan 06, 2026
Response Filed
Feb 26, 2026
Final Rejection — §102 (current)

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+9.3%)
2y 9m
Median Time to Grant
Moderate
PTA Risk
Based on 1083 resolved cases by this examiner. Grant probability derived from career allow rate.

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