DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 7/9/2026 is acknowledged.
Applicant amended claims 1 and 19; and cancelled claim 8.
Applicant added claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0233906) (hereafter Chen), in view of Xie et al. (US 2023/0139929) (hereafter Xie929), in further view of Xie et al. (US 2023/0178433) (hereafter Xie433).
Regarding claim 19, Chen discloses a semiconductor device comprising:
first 107A (Fig. 1L, paragraph 0035) and second active regions 108A (Fig. 1L, paragraph 0035) on a substrate 106 (Fig. 1L, paragraph 0035) and extending longitudinally (see 107 and 108 extending in horizontal direction in Fig. 1J) in a first direction (horizontal direction in Fig. 1J);
a first gate structure 112C (Fig. 1L, paragraph 0032) and a second gate structure 112E (Fig. 1L, paragraph 0032) on the first 107A (Fig. 1L) and second active regions 108A (Fig. 1L), respectively, wherein the first 112C (Fig. 1L) and second gate structures 112E (Fig. 1L) extend (see 112C and 112E extending in vertical direction in Fig. 1J) in a second direction (vertical direction in Fig. 1J) and are spaced apart from each other in the second direction (vertical direction in Fig. 1J);
first 107B (Fig. 1M, paragraph 0035) and second source/drain regions 108B (Fig. 1M, paragraph 0035) on the first 107A (Fig. 1M) and second active regions 108A (Fig. 1M), respectively, and adjacent (see Figs. 1J and 1M) to the first 112C (Fig. 1J) and second gate structures 112E (Fig. 1J); and
first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M).
Chen does not disclose a vertical buried structure including a conductive material and comprising first and second side surfaces that are spaced apart from each other in the second direction, wherein the first contact plug comprises a surface facing, in the second direction, the first side surface of the vertical buried structure and contacting an upper portion of the first side surface; and
a horizontal buried structure contacting a lower surface of the vertical buried structure,
wherein an uppermost end of the vertical buried structure is farther than an uppermost end of the first source/drain region from the substrate.
Xie929 discloses a vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) including a conductive material (“contact conductor material” in paragraph 0077) and comprising first (left surface of right portion of 46B in Fig. 12B) and second side surfaces (right surface of right portion of 46B in Fig. 12B) that are spaced apart from each other in the second direction (horizontal direction in Fig. 12B), wherein the first contact plug (left portion of 46B in Fig. 12B) comprises a surface (right surface of left portion of 46B in Fig. 12B) facing, in the second direction (horizontal direction in Fig. 12B), the first side surface (left surface of right portion of 46B in Fig. 12B) of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) and contacting an upper portion of the first side surface (left surface of right portion of 46B in Fig. 12B); and
a horizontal buried structure 16 (Fig. 12B, paragraph 0032) contacting a lower surface of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C),
wherein an uppermost end of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) is farther than an uppermost end of the first source/drain region (left 26 in Fig. 12B, paragraph 0033) from the substrate 10 (Fig. 12B, paragraph 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form a vertical buried structure including a conductive material and comprising first and second side surfaces that are spaced apart from each other in the second direction, wherein the first contact plug comprises a surface facing, in the second direction, the first side surface of the vertical buried structure and contacting an upper portion of the first side surface; and a horizontal buried structure contacting a lower surface of the vertical buried structure, wherein an uppermost end of the vertical buried structure is farther than an uppermost end of the first source/drain region from the substrate, as taught by Xie929, since VBPR contact structure (Xie929, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie929, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Chen and Xie929 do not disclose a side surface of the conductive material of the vertical buried structure extends farther from the substrate than the first source/drain region and extends closer to the substrate than the first source/drain region.
Xie433 discloses a side surface (side surface of 56 in Fig. 14) of the conductive material (see paragraph 0060) of the vertical buried structure 56 (Fig. 14, paragraph 0058) extends farther from the substrate 10 (Fig. 14, paragraph 0036) than the first source/drain region 50 (Fig. 14, paragraph 0058) and extends closer to the substrate 10 (Fig. 14) than the first source/drain region 50 (Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen in view of Xie929 to form a side surface of the conductive material of the vertical buried structure extends farther from the substrate than the first source/drain region and extends closer to the substrate than the first source/drain region, as taught by Xie433, since source/drain contacts (CA) (Xie433, paragraph 0006) disposed adjacent via-to buried power rail (VBPR) contacts and source/drain regions collectively defining middle-of-line (MOL) components.
Regarding claim 20, Chen in view of Xie929 and Xie433 discloses the semiconductor device of claim 19, however Chen does not disclose the vertical buried structure extends between the first and second gate structures in the first direction.
Xie929 discloses the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) extends between the first (left 40 in Fig. 12C, paragraph 0062) and second gate structures (right 40 in Fig. 12C, paragraph 0062) in the first direction (horizontal direction in Fig. 12C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form the vertical buried structure extends between the first and second gate structures in the first direction, as taught by Xie929, since VBPR contact structure (Xie929, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie929, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Allowable Subject Matter
1. Claims 1-7 and 9-18 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Chen et al. (US 2021/0233906), discloses first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) but fails to disclose the first contact plug comprises first and second end portions that are spaced apart from each other in the second direction, and wherein the first end portion of the first contact plug is in the vertical buried structure, in a plan view. Additionally, the prior art does not teach or suggest a semiconductor device comprising: the first contact plug comprises first and second end portions that are spaced apart from each other in the second direction, and wherein the first end portion of the first contact plug is in the vertical buried structure, in a plan view in combination with other elements of claim 1.
In addition, a closest prior art, Chen et al. (US 2021/0233906), discloses a vertical buried structure 104* (Fig. 1M, paragraph 0032) between the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M), wherein the vertical buried structure 104* (Fig. 1J) comprises first (top surface of 104* in Fig. 1J) and second side surfaces (bottom surface of 104* in Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J), and the first contact plug (first 122 from the left corner of Fig. 1J) contacts the first side surface (top surface of 104* in Fig. 1J) of the vertical buried structure 104* (Fig. 1J), and wherein the first contact plug (first 122 from the left corner of Fig. 1J) comprises first (top surface of first 122 from the left corner of Fig. 1J) and second end portions (bottom surface of first 122 from the left corner of Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J) but fails to disclose the first end portion of the first contact plug is in the vertical buried structure, in a plan view. Additionally, the prior art does not teach or suggest a semiconductor device comprising: the first end portion of the first contact plug is in the vertical buried structure, in a plan view in combination with other elements of claim 14.
A closest prior art, Chen et al. (US 2021/0233906), discloses a semiconductor device comprising: first 107A (Fig. 1L, paragraph 0035) and second active regions 108A (Fig. 1L, paragraph 0035) on a substrate 106 (Fig. 1L, paragraph 0035) and extending longitudinally (see 107 and 108 extending in horizontal direction in Fig. 1J) in a first direction (horizontal direction in Fig. 1J); a first gate structure 112C (Fig. 1L, paragraph 0032) and a second gate structure 112E (Fig. 1L, paragraph 0032) on the first 107A (Fig. 1L) and second active regions 108A (Fig. 1L), respectively, wherein the first 112C (Fig. 1L) and second gate structures 112E (Fig. 1L) extend (see 112C and 112E extending in vertical direction in Fig. 1J) in a second direction (vertical direction in Fig. 1J) and are spaced apart from each other in the second direction (vertical direction in Fig. 1J); first 107B (Fig. 1M, paragraph 0035) and second source/drain regions 108B (Fig. 1M, paragraph 0035) on the first 107A (Fig. 1M) and second active regions 108A (Fig. 1M), respectively, and adjacent (see Figs. 1J and 1M) to the first 112C (Fig. 1J) and second gate structures 112E (Fig. 1J); and first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) but fails to teach a vertical buried structure between the first and second gate structures and between the first and second source/drain regions and including a conductive material; wherein the vertical buried structure comprises first and second side surfaces spaced apart from each other in the second direction, and the first contact plug contacts the first side surface of the vertical buried structure, wherein the vertical buried structure separates, in the second direction, the first contact plug from the second contact plug; and wherein the first contact plug comprises first and second end portions that are spaced apart from each other in the second direction, and wherein the first end portion of the first contact plug is in the vertical buried structure, in a plan view as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-7 and 9-13 depend on claim 1.
In addition, a closest prior art, Chen et al. (US 2021/0233906), discloses a semiconductor device comprising: first 107A (Fig. 1L, paragraph 0035) and second active regions 108A (Fig. 1L, paragraph 0035) on a substrate 106 (Fig. 1L, paragraph 0035) and extending longitudinally (see 107 and 108 extending in horizontal direction in Fig. 1J) in a first direction (horizontal direction in Fig. 1J); a first gate structure 112C (Fig. 1L, paragraph 0032) and a second gate structure 112E (Fig. 1L, paragraph 0032) on the first 107A (Fig. 1L) and second active regions 108A (Fig. 1L), respectively, wherein the first 112C (Fig. 1L) and second gate structures 112E (Fig. 1L) extend (see 112C and 112E extending in vertical direction in Fig. 1J) in a second direction (vertical direction in Fig. 1J) and are spaced apart from each other in the second direction (vertical direction in Fig. 1J); first 107B (Fig. 1M, paragraph 0035) and second source/drain regions 108B (Fig. 1M, paragraph 0035) on the first 107A (Fig. 1M) and second active regions 108A (Fig. 1M), respectively, and adjacent (see Figs. 1J and 1M) to the first 112C (Fig. 1J) and second gate structures 112E (Fig. 1J); first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M); and a vertical buried structure 104* (Fig. 1M, paragraph 0032) between the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M), wherein the vertical buried structure 104* (Fig. 1J) comprises first (top surface of 104* in Fig. 1J) and second side surfaces (bottom surface of 104* in Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J), and the first contact plug (first 122 from the left corner of Fig. 1J) contacts the first side surface (top surface of 104* in Fig. 1J) of the vertical buried structure 104* (Fig. 1J), and wherein the first contact plug (first 122 from the left corner of Fig. 1J) comprises first (top surface of first 122 from the left corner of Fig. 1J) and second end portions (bottom surface of first 122 from the left corner of Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J) but fails to teach the first end portion of the first contact plug is in the vertical buried structure, in a plan view as the context of claim 14. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 15-18 depend on claim 14.
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
4. Claim 21 would be allowable because a closest prior art, Chen et al. (US 2021/0233906), discloses first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) but fails to disclose the limitations of the claim that recites a semiconductor device comprising: a vertical buried structure including a conductive material and comprising first and second side surfaces that are spaced apart from each other in the second direction, wherein the first contact plug comprises a surface facing, in the second direction, the first side surface of the vertical buried structure and contacting an upper portion of the first side surface; and wherein the first contact plug and the first side surface of the vertical buried structure form an interfacial surface having a plurality of curvatures. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device comprising: the first contact plug and the first side surface of the vertical buried structure form an interfacial surface having a plurality of curvatures in combination with other elements of the base claim 19.
Response to Arguments
1. Applicant's arguments filed 7/9/2026 have been fully considered.
2. Applicant's arguments with respect to claims 19 and 20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
