DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 2/23/2026 is acknowledged.
Applicant amended claims 1 and 19.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/19/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, 11, 12, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0233906) (hereafter Chen), in view of Xie et al. (US 2023/0139929) (hereafter Xie).
Regarding claim 1, Xie discloses a semiconductor device comprising:
first 107A (Fig. 1L, paragraph 0035) and second active regions 108A (Fig. 1L, paragraph 0035) on a substrate 106 (Fig. 1L, paragraph 0035) and extending longitudinally (see 107 and 108 extending in horizontal direction in Fig. 1J) in a first direction (horizontal direction in Fig. 1J);
a first gate structure 112C (Fig. 1L, paragraph 0032) and a second gate structure 112E (Fig. 1L, paragraph 0032) on the first 107A (Fig. 1L) and second active regions 108A (Fig. 1L), respectively, wherein the first 112C (Fig. 1L) and second gate structures 112E (Fig. 1L) extend (see 112C and 112E extending in vertical direction in Fig. 1J) in a second direction (vertical direction in Fig. 1J) and are spaced apart from each other in the second direction (vertical direction in Fig. 1J);
first 107B (Fig. 1M, paragraph 0035) and second source/drain regions 108B (Fig. 1M, paragraph 0035) on the first 107A (Fig. 1M) and second active regions 108A (Fig. 1M), respectively, and adjacent (see Figs. 1J and 1M) to the first 112C (Fig. 1J) and second gate structures 112E (Fig. 1J); and
first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M).
Chen does not disclose a vertical buried structure between the first and second gate structures and between the first and second source/drain regions and including a conductive material;
wherein the vertical buried structure comprises first and second side surfaces spaced apart from each other in the second direction, and the first contact plug contacts the first side surface of the vertical buried structure, and
wherein the vertical buried structure separates, in the second direction, the first contact plug from the second contact plug.
Xie discloses a vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) between the first (left 40 in Fig. 12C) and second gate structures (right 40 in Fig. 12C) and between the first (left 26 in Fig. 12B, paragraph 0084) and second source/drain regions (right 26 in Fig. 12B, paragraph 0084) and including a conductive material (“contact conductor material” in paragraph 0077);
wherein the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) comprises first (left surface of right portion of 46B in Fig. 12B) and second side surfaces (right surface of right portion of 46B in Fig. 12B) spaced apart from each other in the second direction (horizontal direction in Fig. 12B), and the first contact plug (left portion of 46B in Fig. 12B) contacts (region where left portion of 46B and right portion of 46B are connected in Fig. 12B) the first side surface (left surface of right portion of 46B in Fig. 12B) of the vertical buried structure, and
wherein the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) separates, in the second direction (horizontal direction in Fig. 12B), the first contact plug (left portion of 46B in Fig. 12B) from the second contact plug 46A (Fig. 12B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form a vertical buried structure between the first and second gate structures and between the first and second source/drain regions and including a conductive material; wherein the vertical buried structure comprises first and second side surfaces spaced apart from each other in the second direction, and the first contact plug contacts the first side surface of the vertical buried structure, and wherein the vertical buried structure separates, in the second direction, the first contact plug from the second contact plug, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Regarding claim 2, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen does not disclose an uppermost end of the vertical buried structure is farther than an uppermost end of the first source/drain region from the substrate.
Xie discloses an uppermost end of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) is farther than an uppermost end of the first source/drain region (left 26 in Fig. 12B, paragraph 0033) from the substrate 10 (Fig. 12B, paragraph 0036).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form an uppermost end of the vertical buried structure is farther than an uppermost end of the first source/drain region from the substrate, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Regarding claim 3, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen does not disclose a lowermost end of the vertical buried structure is closer than a lowermost end of the first source/drain region to a bottom of the substrate.
Xie discloses a lowermost end of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) is closer than a lowermost end of the first source/drain region (left 26 in Fig. 12B, paragraph 0033) to a bottom of the substrate 10 (Fig. 12B, paragraph 0036).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form a lowermost end of the vertical buried structure is closer than a lowermost end of the first source/drain region to a bottom of the substrate, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Regarding claim 4, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen does not disclose the substrate is equidistant from an uppermost end of the vertical buried structure and an uppermost end of the first contact plug.
Xie discloses the substrate 10 (Fig. 12B, paragraph 0036) is equidistant from an uppermost end of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) and an uppermost end of the first contact plug (left portion of 46B in Fig. 12B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form the substrate is equidistant from an uppermost end of the vertical buried structure and an uppermost end of the first contact plug, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Regarding claim 9, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen does not disclose an upper portion of the first contact plug overlaps the vertical buried structure in a third direction that is perpendicular to the first and second directions.
Xie discloses an upper portion of the first contact plug (left portion of 46B in Fig. 12B) overlaps the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) in a third direction (vertical direction in Fig. 12B) that is perpendicular to the first (horizontal direction in Fig. 12B) and second directions (stacking direction in Fig. 12B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form an upper portion of the first contact plug overlaps the vertical buried structure in a third direction that is perpendicular to the first and second directions, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Regarding claim 11, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen does not disclose a vertical insulating layer extending on a side surface of the vertical buried structure.
Xie discloses a vertical insulating layer 28 (Fig. 12B, paragraph 0034) extending on a side surface of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form a vertical insulating layer extending on a side surface of the vertical buried structure, as taught by Xie, since a vertical insulating layer/interlayer dielectric material layer 28 (Xie, Fig. 12B, paragraph 0034) electrically isolates between contact structures.
Regarding claim 12, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen does not disclose a horizontal buried structure contacting a lower surface of the vertical buried structure.
Xie discloses a horizontal buried structure 16 (Fig. 12B, paragraph 0038) contacting a lower surface of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form a horizontal buried structure contacting a lower surface of the vertical buried structure, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Regarding claim 19, Chen discloses a semiconductor device comprising:
first 107A (Fig. 1L, paragraph 0035) and second active regions 108A (Fig. 1L, paragraph 0035) on a substrate 106 (Fig. 1L, paragraph 0035) and extending longitudinally (see 107 and 108 extending in horizontal direction in Fig. 1J) in a first direction (horizontal direction in Fig. 1J);
a first gate structure 112C (Fig. 1L, paragraph 0032) and a second gate structure 112E (Fig. 1L, paragraph 0032) on the first 107A (Fig. 1L) and second active regions 108A (Fig. 1L), respectively, wherein the first 112C (Fig. 1L) and second gate structures 112E (Fig. 1L) extend (see 112C and 112E extending in vertical direction in Fig. 1J) in a second direction (vertical direction in Fig. 1J) and are spaced apart from each other in the second direction (vertical direction in Fig. 1J);
first 107B (Fig. 1M, paragraph 0035) and second source/drain regions 108B (Fig. 1M, paragraph 0035) on the first 107A (Fig. 1M) and second active regions 108A (Fig. 1M), respectively, and adjacent (see Figs. 1J and 1M) to the first 112C (Fig. 1J) and second gate structures 112E (Fig. 1J); and
first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M).
Chen does not disclose a vertical buried structure including a conductive material and comprising first and second side surfaces that are spaced apart from each other in the second direction, wherein the first contact plug comprises a surface facing, in the second direction, the first side surface of the vertical buried structure and contacting an upper portion of the first side surface; and
a horizontal buried structure contacting a lower surface of the vertical buried structure,
wherein an uppermost end of the vertical buried structure is farther than an uppermost end of the first source/drain region from the substrate.
Xie discloses a vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) including a conductive material (“contact conductor material” in paragraph 0077) and comprising first (left surface of right portion of 46B in Fig. 12B) and second side surfaces (right surface of right portion of 46B in Fig. 12B) that are spaced apart from each other in the second direction (horizontal direction in Fig. 12B), wherein the first contact plug (left portion of 46B in Fig. 12B) comprises a surface (right surface of left portion of 46B in Fig. 12B) facing, in the second direction (horizontal direction in Fig. 12B), the first side surface (left surface of right portion of 46B in Fig. 12B) of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) and contacting an upper portion of the first side surface (left surface of right portion of 46B in Fig. 12B); and
a horizontal buried structure 16 (Fig. 12B, paragraph 0032) contacting a lower surface of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C),
wherein an uppermost end of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) is farther than an uppermost end of the first source/drain region (left 26 in Fig. 12B, paragraph 0033) from the substrate 10 (Fig. 12B, paragraph 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form a vertical buried structure including a conductive material and comprising first and second side surfaces that are spaced apart from each other in the second direction, wherein the first contact plug comprises a surface facing, in the second direction, the first side surface of the vertical buried structure and contacting an upper portion of the first side surface; and a horizontal buried structure contacting a lower surface of the vertical buried structure, wherein an uppermost end of the vertical buried structure is farther than an uppermost end of the first source/drain region from the substrate, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Regarding claim 20, Chen in view of Xie discloses the semiconductor device of claim 19, however Chen does not disclose the vertical buried structure extends between the first and second gate structures in the first direction.
Xie discloses the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C) extends between the first (left 40 in Fig. 12C, paragraph 0062) and second gate structures (right 40 in Fig. 12C, paragraph 0062) in the first direction (horizontal direction in Fig. 12C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form the vertical buried structure extends between the first and second gate structures in the first direction, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Xie as applied to claim 1 above, and further in view of Shue et al. (US 2012/0322261) (hereafter Shue).
Regarding claim 5, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen and Xie do not disclose an upper portion of the first side surface of the vertical buried structure and an upper portion of the second side surface of the vertical buried structure have different degrees of inclination.
Shue discloses an upper portion (upper left surface of 66 in Fig. 12) of the first side surface (left surface of 66 in Fig. 12) of the vertical buried structure 66 (Fig. 12, paragraph 0031) and an upper portion (right surface of 66 at 76 in Fig. 12) of the second side surface (right surface of 66 in Fig. 12) of the vertical buried structure 66 (Fig. 12) have different degrees of inclination.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen in view of Xie to form an upper portion of the first side surface of the vertical buried structure and an upper portion of the second side surface of the vertical buried structure have different degrees of inclination, as taught by Shue, since rounded interface regions 76 (Shue, Fig. 12, paragraph 0032) between the via 68 and the conductive line 66 further contribute to the reduction of the current crowding effects.
Claims 6, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Xie as applied to claim 1 above, and further in view of Kim et al. (US 2021/0028112) (hereafter Kim).
Regarding claim 6, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen does not disclose the first contact plug contacts an upper portion of the first side surface of the vertical buried structure.
Xie discloses the first contact plug (left portion of 46B in Fig. 12B) contacts (region where left portion of 46B and right portion of 46B are connected in Fig. 12B) an upper portion of the first side surface (left surface of right portion of 46B in Fig. 12B) of the vertical buried structure (right portion of 46B in Fig. 12B and 46B in Fig. 12C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form the first contact plug contacts an upper portion of the first side surface of the vertical buried structure, as taught by Xie, since VBPR contact structure (Xie, paragraph 0005) is present that has a via portion contacting a buried power rail or a backside power rail and a non-via portion contacting a source/drain region of a first functional gate structure in order to improve (Xie, paragraph 0004) the scaling and reduce the routing complexity of the signal lines.
Chen and Xie do not disclose an uppermost end of the vertical buried structure is closer than an uppermost end of the first contact plug to the substrate.
Kim discloses an uppermost end of the vertical buried structure (180B, 120, and 250 in Fig. 2) is closer than an uppermost end of the first contact plug (180A, V1, and M1 in Fig. 2, paragraph 0049) to the substrate 272 (Fig. 2, paragraph 0124).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen in view of Xie to form an uppermost end of the vertical buried structure is closer than an uppermost end of the first contact plug to the substrate, as taught by Kim, since each of the metal vias V1 (Kim, Fig. 2, paragraph 0046) may be formed at a contact to be connected to the contact structure 180 (Kim, Fig. 2, paragraph 0046) in the metal wiring M1 (Kim, Fig. 2, paragraph 0046) and the first wiring portion ML1 (Kim, Fig. 2, paragraph 0048) may be configured to interconnect a plurality of devices (e.g., transistors).
Regarding claim 7, Chen further discloses the semiconductor device of claim 1, wherein the first contact plug (first 122 from the left corner of Fig. 1J) has a first length (horizontal length of first 122 from the left corner of Fig. 1J) in the first direction (horizontal direction in Fig. 1J) and has a second length (vertical length of first 122 from the left corner of Fig. 1J) in the second direction (vertical direction in Fig. 1J), and the second length (vertical length of first 122 from the left corner of Fig. 1K) is longer than the first length (horizontal length of first 122 from the left corner of Fig. 1K).
Chen and Xie do not disclose the vertical buried structure has a third length in the first direction and has a fourth length in the second direction, and the fourth length is shorter than the third length.
Kim discloses the vertical buried structure (120 and 250 in Fig. 4A, paragraph 0052) has a third length (vertical length of 120 and 250 in Fig. 4A) in the first direction (vertical direction in Fig. 4A) and has a fourth length (horizontal length of 120 and 250 in Fig. 4A) in the second direction (horizontal direction in Fig. 4A), and the fourth length (horizontal length of 120 and 250 in Fig. 4A) is shorter (see paragraph 0052, wherein “a cross-section of the conductive through structure 250 may have a substantially rectangular shape, and may have a shape by which a distance or dimension in the first direction is greater than a distance or dimension in the second direction, perpendicular thereto”) than the third length (vertical length of 120 and 250 in Fig. 4A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen in view of Xie to form the vertical buried structure has a third length in the first direction and has a fourth length in the second direction, and the fourth length is shorter than the third length, as taught by Kim, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 10, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen and Xie do not disclose a width of the vertical buried structure in the second direction is in a range of about 10 nanometers (nm) to about 40 nm.
Kim discloses a width of the vertical buried structure (180B, 120, and 250 in Fig. 2, paragraph 0039, wherein “20 nm to 500 nm”) in the second direction is in a range of 20 nm to 500 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen in view of Xie to form a width of the vertical buried structure in the second direction is in a range of about 10 nanometers (nm) to about 40 nm, as taught by Kim, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Xie as applied to claim 1 above, and further in view of Lim et al. (US 2021/0036121) (hereafter Lim).
Regarding claim 13, Chen in view of Xie discloses the semiconductor device of claim 1, however Chen and Xie do not disclose a plurality of channel layers on the first active region, wherein the plurality of channel layers are spaced apart from each other in a third direction that is perpendicular to the first and second directions and are in the first gate structure.
Lim discloses a plurality of channel layers 140 (Fig. 6, paragraph 0033) on the first active region (105 of TR1 in Fig. 6, paragraph 0033), wherein the plurality of channel layers 140 (Fig. 6) are spaced apart from each other in a third direction (vertical direction in Fig. 6) that is perpendicular to the first (horizontal direction in Fig. 6) and second directions (stacking direction in Fig. 6) and are in the first gate structure (left 160 in Fig. 6, paragraph 0033).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen in view of Xie to form a plurality of channel layers on the first active region, wherein the plurality of channel layers are spaced apart from each other in a third direction that is perpendicular to the first and second directions and are in the first gate structure, as taught by Lim, since the integration density (Lim, paragraph 0003) of semiconductor devices has increased.
Allowable Subject Matter
1. Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 8 would be allowable because a closest prior art, Chen et al. (US 2021/0233906), discloses first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) but fails to disclose the first end portion of the first contact plug is in the vertical buried structure, in a plan view. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device comprising: the first end portion of the first contact plug is in the vertical buried structure, in a plan view in combination with other elements of the base claim 1.
Claims 14-18 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Chen et al. (US 2021/0233906), discloses a vertical buried structure 104* (Fig. 1M, paragraph 0032) between the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M), wherein the vertical buried structure 104* (Fig. 1J) comprises first (top surface of 104* in Fig. 1J) and second side surfaces (bottom surface of 104* in Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J), and the first contact plug (first 122 from the left corner of Fig. 1J) contacts the first side surface (top surface of 104* in Fig. 1J) of the vertical buried structure 104* (Fig. 1J), and wherein the first contact plug (first 122 from the left corner of Fig. 1J) comprises first (top surface of first 122 from the left corner of Fig. 1J) and second end portions (bottom surface of first 122 from the left corner of Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J) but fails to disclose the first end portion of the first contact plug is in the vertical buried structure, in a plan view. Additionally, the prior art does not teach or suggest a semiconductor device comprising: the first end portion of the first contact plug is in the vertical buried structure, in a plan view in combination with other elements of claim 14.
A closest prior art, Chen et al. (US 2021/0233906), discloses a semiconductor device comprising: first 107A (Fig. 1L, paragraph 0035) and second active regions 108A (Fig. 1L, paragraph 0035) on a substrate 106 (Fig. 1L, paragraph 0035) and extending longitudinally (see 107 and 108 extending in horizontal direction in Fig. 1J) in a first direction (horizontal direction in Fig. 1J); a first gate structure 112C (Fig. 1L, paragraph 0032) and a second gate structure 112E (Fig. 1L, paragraph 0032) on the first 107A (Fig. 1L) and second active regions 108A (Fig. 1L), respectively, wherein the first 112C (Fig. 1L) and second gate structures 112E (Fig. 1L) extend (see 112C and 112E extending in vertical direction in Fig. 1J) in a second direction (vertical direction in Fig. 1J) and are spaced apart from each other in the second direction (vertical direction in Fig. 1J); first 107B (Fig. 1M, paragraph 0035) and second source/drain regions 108B (Fig. 1M, paragraph 0035) on the first 107A (Fig. 1M) and second active regions 108A (Fig. 1M), respectively, and adjacent (see Figs. 1J and 1M) to the first 112C (Fig. 1J) and second gate structures 112E (Fig. 1J); first (first 122 from the left corner of Fig. 1J, paragraph 0043) and second contact plugs (second 122 from the left corner of Fig. 1J, paragraph 0043) on (see Fig. 1J, wherein first 122 and second 122 from the left corner of Fig. 1J are on 107 and 108; and see Fig. 1M, wherein 122 is on 107B and 108B such that first 122 from the left corner of Fig. 1J forms on 107B which is formed between 112A and 112B) the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M) and respectively connected to the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M); and a vertical buried structure 104* (Fig. 1M, paragraph 0032) between the first 107B (Fig. 1M) and second source/drain regions 108B (Fig. 1M), wherein the vertical buried structure 104* (Fig. 1J) comprises first (top surface of 104* in Fig. 1J) and second side surfaces (bottom surface of 104* in Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J), and the first contact plug (first 122 from the left corner of Fig. 1J) contacts the first side surface (top surface of 104* in Fig. 1J) of the vertical buried structure 104* (Fig. 1J), and wherein the first contact plug (first 122 from the left corner of Fig. 1J) comprises first (top surface of first 122 from the left corner of Fig. 1J) and second end portions (bottom surface of first 122 from the left corner of Fig. 1J) that are spaced apart from each other in the second direction (vertical direction in Fig. 1J) but fails to teach the first end portion of the first contact plug is in the vertical buried structure, in a plan view as the context of claim 14. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 15-18 depend on claim 14.
Response to Arguments
1. Applicant's arguments filed 2/23/2026 have been fully considered.
2. Applicant's arguments with respect to claims 1-7, 9-13, 19, and 20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813