DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, line 6, the recitation of “comprises” should be changed to “comprise”, for clarity.
In claim 20, line 1, the recitation of “3D” should be changed to “three-dimensional (3D)”, for clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2018/0102316).
Regarding claim 1, Choi discloses, as shown in Figures 1B, 1C and 3A, a three-dimensional (3D) memory device comprising a memory array (12, MCA), wherein the memory array comprises:
a first multi-layer stacked structure, wherein the first multi-layer stacked structure comprises alternately stacked dielectric layers (176) and conductive layers (GSL, WL1, WL2, …, WLn);
first capacitor structures (MOS capacitors) penetrating the first multi-layer stacked structure, wherein the first capacitor structures comprise a dielectric layer (184) and an electrode layer (180), wherein the dielectric layer of a first capacitor structure is disposed between the electrode layer (180) of the first capacitor structure and the dielectric layers (176) or the conductive layers (GSL, WL1, WL2, …, WLn) of the first multi-layer stacked structure; and
a blocking structure (CSL, 192) penetrating the first multi-layer stacked structure (WLC), wherein the blocking structure separates one subset of the first capacitor structures from another subset of the first capacitor structures, and wherein the blocking structure comprises a dielectric layer (192) and a conductive layer (CSL).
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (US 2022/0189958).
Regarding claim 1, Choi discloses, as shown in Figures 1B and 3, a three-dimensional (3D) memory device comprising a memory array, wherein the memory array comprises:
a first multi-layer stacked structure (31,32), wherein the first multi-layer stacked structure comprises alternately stacked dielectric layers (31, [0035]) and conductive layers (32, [0035]);
first capacitor structures (C1) penetrating the first multi-layer stacked structure, wherein the first capacitor structures comprise a dielectric layer (CM1, CI1) and an electrode layer (CAP1), wherein the dielectric layer of a first capacitor structure is disposed between the electrode layer (CAP1) of the first capacitor structure and the dielectric layers (31) or the conductive layers (32) of the first multi-layer stacked structure; and
a blocking structure (SUP) penetrating the first multi-layer stacked structure, wherein the blocking structure separates one subset of the first capacitor structures (C1) from another subset of the first capacitor structures (C2), and wherein the blocking structure comprises a dielectric layer (SCM, SCI) and a conductive layer (CC).
Regarding claim 2, Choi discloses the dielectric layers (CM1 CI1) of the first capacitor structure and the dielectric layer (SCM, SCI) of the blocking structure comprises a same dielectric material (see Figures 2F-2O, forming of the same dielectric layers, so they have the same dielectric material); and
the electrode layers (CAP1) of the first capacitor structures and the conductive layer (CC) of the blocking structure comprise a same conductive material (see Figures 2F-2O, forming of the same layers, so they have the same conductive material.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0189958) in view of Lee et al. (US 2022/0199621).
Choi discloses the claimed invention including the semiconductor device as explained in the above rejection. Choi further discloses the dielectric layers (CM1 CI1) of the first capacitor structure and the dielectric layer (SCM, SCI) of the blocking structure comprises a same dielectric material (see Figures 2F-2O, forming of the same dielectric layers, so they have the same dielectric material). Choi does not disclose the dielectric layer of each of the first capacitor structures and the dielectric layer of the blocking structure comprise a ferroelectric material or an anti-ferroelectric material. However, Lee et al. discloses a dielectric layer (DL) of each of the first capacitor structures comprises a ferroelectric material. Note Figures 9A-11B and [0055] of Lee et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the dielectric layer of each of the first capacitor structures and the dielectric layer of the blocking structure of Choi comprise a ferroelectric material, such as taught by Lee et al. in order to further improve the capacitance of the capacitor.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0189958) in view of Yamazaki et al. (PN 5,176,789).
Choi discloses the claimed invention including the semiconductor device as explained in the above rejection. Choi does not disclose the blocking structure further comprises a dielectric filling material, and wherein the conductive layer of the blocking structure is disposed between the dielectric layer of the blocking structure and the dielectric filling material. However, Yamazaki et al. discloses a blocking structure the blocking structure comprises a dielectric filling material (6), and wherein the conductive layer (5) of the blocking structure is disposed between the dielectric layer (4) of the blocking structure and the dielectric filling material (6). Note Figures 4(A)-4(C) of Yamazaki et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the blocking structure of Choi having the conductive layer is disposed between the dielectric layer and the dielectric filling material, such as taught by Yamazaki et al. in order to further improve isolation between the memory cells.
Claim(s) 5-6, 10-12 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0189958) in view of Nishikawa et al. (PN 10,629,675).
Regarding claim 5, Choi discloses the claimed invention including the semiconductor device as explained in the above rejection. Choi does not disclose the memory array further comprises a second multi-layer stacked structure over the first multi-layer stacked structure, wherein the second multi-layer stacked structure comprises a first insulating layer, a word line layer over the first insulating layer, and a second insulating layer over the word line layer. However, Nishikawa et al. discloses a memory array comprising a second multi-layer stacked structure (232,242,265,270,72) over the first multi-layer stacked structure (132,142,165,170), wherein the second multi-layer stacked structure comprises a first insulating layer, a word line layer over the first insulating layer, and a second insulating layer over the word line layer. Note Figures of Nishikawa et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the memory array of Choi further comprising a second multi-layer stacked structure over the first multi-layer stacked structure, wherein the second multi-layer stacked structure comprises a first insulating layer, a word line layer over the first insulating layer, and a second insulating layer over the word line layer, such as taught by Nishikawa et al. in order to further integrate more memories to achieve more density circuitry.
Regarding claim 6, Choi and Nishikawa et al. disclose the memory array further comprises:
second capacitor structures (245) penetrating the second multi-layer stacked structure, wherein the second capacitor structures are disposed over the first capacitor structures (145), and wherein each of the second capacitor structure comprises a dielectric layer (232) and a conductive filling material (246); and
bit lines (98) over the second multi-layer stacked structure, wherein the bit lines are disposed over the second capacitor structures (Figure 23).
Regarding claim 10, Choi and Nishikawa et al. disclose the memory array further comprises:
a contact (229,249,269) penetrating the second multi-layer stacked structure, wherein the contact is disposed over the blocking structure, wherein the contact penetrates through the second insulating layer of the second multi-layer stacked structure to the word line layer of the second multi-layer stacked structure, and wherein the contact is in contact with the word line layer of the second multi-layer stacked structure (Figures 7A and 21A-24 of Nishikawa et al.)
Regarding claim 11, Choi and Nishikawa et al. disclose more than one contacts (229,249,269) are disposed over a respective blocking structure (Figures 7A and 21A-24.)
Regarding claim 12, Choi and Nishikawa et al. disclose the memory array comprises a plurality of blocking structures (79,76), wherein a contact is disposed at a first subset of the blocking structures, and wherein no contact is disposed at a second subset of the blocking structures (Figure 22).
Regarding claim 14, Choi discloses, as shown in Figures 1B and 3, a three-dimensional (3D) memory device comprising a memory array, wherein the memory array comprises:
a first multi-layer stacked structure (31,32), wherein the first multi-layer stacked structure comprises alternately stacked dielectric layers (31, [0035]) and conductive layers (32, [0035]);
first capacitor structures (C1) penetrating the first multi-layer stacked structure;
a blocking structure (SUP) penetrating the first multi-layer stacked structure, wherein the blocking structure separates one subset of the first capacitor structures (C1) from another subset of the first capacitor structures (C2).
Choi does not disclose a second multi-layer stacked structure over the first multi-layer stacked structure, wherein the second multi-layer stacked structure comprises a first insulating layer, a word line layer over the first insulating layer, and a second insulating layer over the word line layer, and a contact penetrating the second multi-layer stacked structure, wherein the contact is disposed over the blocking structure, and wherein the contact is in contact with the word line layer of the second multi-layer stacked structure. However, However, Nishikawa et al. discloses a memory array comprising a second multi-layer stacked structure (232,242,265,270,72) over the first multi-layer stacked structure (132,142,165,170), wherein the second multi-layer stacked structure comprises a first insulating layer (232), a word line layer (246) over the first insulating layer, and a second insulating layer (280,282) over the word line layer, and a contact (229,249,269) penetrating the second multi-layer stacked structure, wherein the contact is disposed over the blocking structure, and wherein the contact is in contact with the word line layer of the second multi-layer stacked structure. Note Figures 7A, 21A-24 of Nishikawa et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the memory array of Choi further comprising a second multi-layer stacked structure over the first multi-layer stacked structure, wherein the second multi-layer stacked structure comprises a first insulating layer, a word line layer over the first insulating layer, and a second insulating layer over the word line layer, and the contact is in contact with the word line layer of the second multi-layer stacked structure, such as taught by Nishikawa et al. in order to further integrate more memories to achieve more density circuitry.
Regarding claim 15, Choi and Nishikawa et al. disclose each of the first capacitor structures comprise a dielectric layer (CM1, CI1) and a conductive layer (CAP1), the dielectric layers (CM1 CI1) of the first capacitor structure and the dielectric layer (SCM, SCI) of the blocking structure comprises a same dielectric material (see Figures 2F-2O, forming of the same dielectric layers, so they have the same dielectric material); and
the electrode layers (CAP1) of the first capacitor structures and the conductive layer (CC) of the blocking structure comprise a same conductive material (see Figures 2F-2O, forming of the same layers, so they have the same conductive material.)
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0189958) in view of Nishikawa et al. (PN 10,629,675) and further in view of Lee et al. (US 2022/0199621).
Regarding claim 16, Choi and Nishikawa et al. disclose the claimed invention including the semiconductor device as explained in the above rejection. Choi and Nishikawa et al. further disclose the dielectric layers (CM1 CI1) of the first capacitor structure and the dielectric layer (SCM, SCI) of the blocking structure comprises a same dielectric material (see Figures 2F-2O, forming of the same dielectric layers, so they have the same dielectric material). Choi and Nishikawa et al. do not disclose the dielectric layer of each of the first capacitor structures and the dielectric layer of the blocking structure comprise a ferroelectric material or an anti-ferroelectric material. However, Lee et al. discloses a dielectric layer (DL) of each of the first capacitor structures comprises a ferroelectric material. Note Figures 9A-11B and [0055] of Lee et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the dielectric layer of each of the first capacitor structures and the dielectric layer of the blocking structure of Choi and Nishikawa et al. comprise a ferroelectric material, such as taught by Lee et al. in order to further improve the capacitance of the capacitor.
Regarding claim 18, Choi, Nishikawa et al. and Lee et al. disclose the memory array further comprises:
second capacitor structures (245) penetrating the second multi-layer stacked structure, wherein the second capacitor structures are disposed over the first capacitor structures (145), and wherein each of the second capacitor structure comprises a dielectric layer (232) and a conductive filling material (246); and
bit lines (98) over the second multi-layer stacked structure, wherein the bit lines are disposed over the second capacitor structures (Figure 23).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0189958) in view of Nishikawa et al. (PN 10,629,675) and further in view of Yamazaki et al. (PN 5,176,789).
Choi and Nishikawa et al. disclose the claimed invention including the semiconductor device as explained in the above rejection. Choi and Nishikawa et al. do not disclose the blocking structure further comprises a dielectric filling material, and wherein the conductive layer of the blocking structure is disposed between the dielectric layer of the blocking structure and the dielectric filling material. However, Yamazaki et al. discloses a blocking structure the blocking structure comprises a dielectric filling material (6), and wherein the conductive layer (5) of the blocking structure is disposed between the dielectric layer (4) of the blocking structure and the dielectric filling material (6). Note Figures 4(A)-4(C) of Yamazaki et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the blocking structure of Choi and Nishikawa et al. having the conductive layer is disposed between the dielectric layer and the dielectric filling material, such as taught by Yamazaki et al. in order to further improve isolation between the memory cells.
Claim(s) 13, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0189958) in view of Huo et al. (US 2021/0104534).
Choi discloses the claimed invention including the semiconductor device as explained in the above rejection. Choi further discloses peripheral circuits are included in the memory system. Cho does not disclose a peripheral circuit bonded to the memory array. However, Huo et al. discloses a memory system having a peripheral circuit (404/408) bonded to a memory array (510). Note Figure 6 and [0074] of Huo et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the memory device of Choi having a peripheral circuit bonded to a memory array, such as taught by Huo et al. in order to further improve the interconnection between the memory array and the peripheral circuit and reduce the overall footprint.
Regarding claim 20, Choi discloses, as shown in Figures 1B and 3, a memory system comprising a three-dimensional (3D) memory device having the memory array comprises:
a first multi-layer stacked structure (31,32), wherein the first multi-layer stacked structure comprises alternately stacked dielectric layers (31, [0035]) and conductive layers (32, [0035]);
first capacitor structures (C1) penetrating the first multi-layer stacked structure, wherein the first capacitor structures comprise a dielectric layer (CM1, CI1) and an electrode layer (CAP1), wherein the dielectric layer of a first capacitor structure is disposed between the electrode layer (CAP1) of the first capacitor structure and the dielectric layers (31) or the conductive layers (32) of the first multi-layer stacked structure; and
a blocking structure (SUP) penetrating the first multi-layer stacked structure, wherein the blocking structure separates one subset of the first capacitor structures (C1) from another subset of the first capacitor structures (C2), and wherein the blocking structure comprises a dielectric layer (SCM, SCI) and a conductive layer (CC).
Choi does not disclose a peripheral circuit bonded to memory array. However, Huo et al. discloses a memory system having a peripheral circuit (404/408) bonded to a memory array (510). Note Figure 6 and [0074] of Huo et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the memory device of Choi having a peripheral circuit bonded to a memory array, such as taught by Huo et al. in order to further improve the interconnection between the memory array and the peripheral circuit and reduce the overall footprint.
Allowable Subject Matter
Claims 7-9 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant' s claims are allowable over the references of record because none of these references disclose or can be combined to yield the claimed 3D memory device having the memory array comprises word line blocking structures penetrating the second multi-layer stacked structure, wherein the word line blocking structures penetrate through at least the second insulating layer of the second multi-layer stacked structure and the word line layer of the second multi-layer stacked structure, as recited in claim 7; none of these references disclose or can be combined to yield the claimed 3D memory device having the memory array comprises word line blocking structures penetrating the second multi-layer stacked structure, wherein the word line blocking structures penetrate through at least the second insulating layer of the second multi-layer stacked structure and the word line layer of the second multi-layer stacked structure, and wherein an extending direction of the word line blocking structures is perpendicular to an extending direction of the blocking structure, as recited in claim 19.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897