Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on April 15, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 15, 2026 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 13-14, 16-20, 22-28, and 30-32 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 2022/0102372).
Claim 13, Choi discloses (Figs. 1 and 2C) a three-dimensional (3D) memory device, comprising: a multi-layer stacked structure (ST, stack, Para [0024]), wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers (11, first conductive layers, Para [0024]) and dielectric layers (12, insulating layers, Para [0024]) along a first direction (11and 12 are alternately stacked along III direction); a semiconductor layer (13, second conductive layer may be polysilicon, Para [0021]) over the multi-layer stacked structure along the first direction (13 are over ST along III direction); and a plurality of channel structures (CH, channel structures, Para [0024]) penetrating into the multi-layer stacked structure and the semiconductor layer along the first direction (CH penetrates ST and 13 in III direction), wherein a first end (under broadest reasonable interpretation (BRI) portion of CH2 end in 13 is considered first end, hereinafter “end1”) of each of the plurality of channel structures (CH) is located within the semiconductor layer (end1 is within 13), and wherein first ends (CH3, third channel structure, Para [0025]) of the plurality of channel structures are aligned with one another along a second direction (CH3 of CH are aligned along with one another along I direction) intersecting with the first direction (I direction intersects with III direction), and the plurality of channel structures are separated from one another along the second direction (CH are separated from each other along I direction), wherein a channel structure (leftmost CH) of the plurality of channel structures (CH) comprises at least a first portion (CH2) and a second portion (CH1) along the first direction (CH2 and CH1 are along III direction), the first portion being in the semiconductor layer (portion of CH2 is in 13) and surrounded by the semiconductor layer along the second direction (portion of CH2 is surrounded by 13 in I direction), and the second portion (CH1) being in the multi-layer stacked structure (CH1 is in ST), and wherein, along the second direction (I direction), the first portion comprises a semiconductor channel layer (25, second channel layer of semiconductor material, Para [0027]) and a channel film (26, gate insulating film, Para [0027]), and the first portion has a smaller critical dimension than the second portion (CH2 has a smaller width than CH1 in I direction).
Claim 14, Choi discloses (Figs. 1 and 2C) the 3D memory device of claim 13, wherein each particular one of the plurality of channel structures (CH) comprises a corresponding first portion (CH2), wherein the corresponding first portion of each particular one of the plurality of channel structures is disposed at a corresponding first end of the particular one of the plurality of channel structures (each corresponding CH2 is disposed at a corresponding end1 of CH) and is surrounded laterally by the semiconductor layer (part of CH2 is surrounded by 13), wherein the corresponding first portion of each particular one of the channel structures has a smaller critical dimension than other portions of the particular one of the channel structures (each corresponding CH2 has a smaller width than a corresponding CH1).
Claim 16, Choi discloses (Figs. 1 and 2C)the 3D memory device of claim 13, wherein each of the plurality of channel structures (CH) comprises a respective dielectric filler layer (17, first insulating core, Para [0036]), a respective semiconductor channel layer (15, first channel layer may be semiconductor, Para [0026]), and a respective channel film (16, memory layer, Para [0026]), and the respective channel film (16) comprises a tunneling layer (16C, tunnel insulating layer, Para [0036]), a storage layer (16B, data storage layer, Para [0036]), and a blocking layer (16A, blocking layer, Para [0036]). Claim 17, Choi discloses (Figs. 1 and 2C)the 3D memory device of claim 16, wherein a top surface of the respective dielectric filler layer (17) of each of the plurality of channel structures (CH) is below a top surface of the respective semiconductor channel layer (15) and the respective channel film (16) of each of the plurality of channel structures (top surface of 17 is below top surfaces of 15 and 16).
Claim 18, Choi discloses (Figs. 1 and 2C)the 3D memory device of claim 13, wherein a dielectric sealing structure (27, second insulating core, Para [0027]) is disposed within each of the plurality of channel structures (27 is disposed within CH) at the first end of each of the plurality of channel structures (27 is within end1), and wherein a respective second semiconductor plug (CP, contact pad which may be polysilicon, Para [0028]) is disposed over the dielectric sealing structure in each of the plurality of channel structures (CP is disposed over each 27 in each CH).
Claim 19, Choi discloses (Figs. 1, 2C, and 17) a system (Fig. 17, 1000, memory system, Para [0085]), comprising: a controller (1100, controller, Para [0085]); and a three-dimensional (3D) memory device (1200, memory device, Para [0085]) coupled to the controller (1200 is coupled to 1100), wherein the controller is configured to control the 3D memory device (1100 controls 1200, Para [0085]), and wherein the 3D memory device (1200) comprises (Figs. 1 and 2C): a multi-layer stacked structure (ST, stack, Para [0024]), wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers (11, first conductive layers, Para [0024]) and dielectric layers (12, insulating layers, Para [0024]) along a first direction (11and 12 are alternately stacked along III direction); a semiconductor layer (13, second conductive layer may be polysilicon, Para [0021]) over the multi-layer stacked structure along the first direction (13 are over ST along III direction); and a plurality of channel structures (CH, channel structures, Para [0024]) penetrating into the multi-layer stacked structure and the semiconductor layer along the first direction (CH penetrates ST and 13 in III direction), wherein a first end (under broadest reasonable interpretation (BRI) portion of CH2 end in 13 is considered first end, hereinafter “end1”) of each of the plurality of channel structures (CH) is located within the semiconductor layer (end1 is within 13), and wherein first ends (CH3, third channel structure, Para [0025]) of the plurality of channel structures are aligned with one another along a second direction (CH3 of CH are aligned along with one another along I direction) intersecting with the first direction (I direction intersects with III direction), and the plurality of channel structures are separated from one another along the second direction (CH are separated from each other along I direction), wherein a channel structure (leftmost CH) of the plurality of channel structures (CH) comprises at least a first portion (CH2) and a second portion (CH1) along the first direction (CH2 and CH1 are along III direction), the first portion being in the semiconductor layer (portion of CH2 is in 13) and surrounded by the semiconductor layer along the second direction (portion of CH2 is surrounded by 13 in I direction), and the second portion (CH1) being in the multi-layer stacked structure (CH1 is in ST), and wherein, along the second direction (I direction), the first portion comprises a semiconductor channel layer (25, second channel layer of semiconductor material, Para [0027]) and a channel film (26, gate insulating film, Para [0027]), and the first portion has a smaller critical dimension than the second portion (CH2 has a smaller width than CH1 in I direction). Claim 20, Choi discloses (Figs. 1, 2C, and 17) the system of claim 19, wherein each particular one of the plurality of channel structures (CH) comprises a corresponding first portion (CH2), wherein the corresponding first portion of each particular one of the plurality of channel structures is disposed at a corresponding first end of the particular one of the plurality of channel structures (each corresponding CH2 is disposed at a corresponding end1 of CH) and is surrounded laterally by the semiconductor layer (part of CH2 is surrounded by 13), wherein the corresponding first portion of each particular one of the channel structures has a smaller critical dimension than other portions of the particular one of the channel structures (each corresponding CH2 has a smaller width than a corresponding CH1).
Claim 22, Choi discloses (Figs. 1, 2C, and 17) the system of claim 19, wherein each of the plurality of channel structures (CH) comprises a respective dielectric filler layer (17, first insulating core, Para [0036]), a respective semiconductor channel layer (15, first channel layer may be semiconductor, Para [0026]), and a respective channel film (16, memory layer, Para [0026]), and the respective channel film (16) comprises a tunneling layer (16C, tunnel insulating layer, Para [0036]), a storage layer (16B, data storage layer, Para [0036]), and a blocking layer (16A, blocking layer, Para [0036]). Claim 23, Choi discloses (Figs. 1, 2C, and 17) the system of claim 22, wherein a top surface of the respective dielectric filler layer (17) of each of the plurality of channel structures (CH) is below a top surface of the respective semiconductor channel layer (15) and the respective channel film (16) of each of the plurality of channel structures (top surface of 17 is below top surfaces of 15 and 16).
Claim 24, Choi discloses (Figs. 1, 2C, and 17) the system of claim 19, wherein a dielectric sealing structure (27, second insulating core, Para [0027]) is disposed within each of the plurality of channel structures (27 is disposed within CH) at the first end of each of the plurality of channel structures (27 is within end1), and wherein a respective second semiconductor plug (CP, contact pad which may be polysilicon, Para [0028]) is disposed over the dielectric sealing structure in each of the plurality of channel structures (CP is disposed over each 27 in each CH).
Claim 25, Choi discloses (Figs. 1, 2C, and 17) the system of claim 19, wherein, along the second direction (I direction), the first portion (CH2) has a same structure as the second portion (CH2 has the same structure 25/26/27 as 15/16/17).
Claim 26, Choi discloses (Figs. 1 and 2C) the 3D memory device of claim 13, wherein, along the second direction (I direction), the first portion (CH2) has a same structure as the second portion (CH2 has the same structure 25/26/27 as 15/16/17). Claim 27, Choi discloses (Figs. 1 and 2C) a method of forming a three-dimensional (3D) memory device, comprising: forming a multi-layer stacked structure (ST, stack, Para [0024]), wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers (11, first conductive layers, Para [0024]) and dielectric layers (12, insulating layers, Para [0024]) along a first direction (11and 12 are alternately stacked along III direction); a semiconductor layer (13, second conductive layer may be polysilicon, Para [0021]) over the multi-layer stacked structure along the first direction (13 are over ST along III direction);and forming a plurality of channel structures (CH, channel structures, Para [0024]) penetrating into the multi-layer stacked structure and the semiconductor layer along the first direction (CH penetrates ST and 13 in III direction), wherein a first end (under broadest reasonable interpretation (BRI) portion of CH2 end in 13 is considered first end, hereinafter “end1”) of each of the plurality of channel structures (CH) is located within the semiconductor layer (end1 is within 13), and wherein first ends (CH3, third channel structure, Para [0025]) of the plurality of channel structures are aligned with one another along a second direction (CH3 of CH are aligned along with one another along I direction) intersecting with the first direction (I direction intersects with III direction), and the plurality of channel structures are separated from one another along the second direction (CH are separated from each other along I direction), wherein a channel structure (leftmost CH) of the plurality of channel structures (CH) comprises at least a first portion (CH2) and a second portion (CH1) along the first direction (CH2 and CH1 are along III direction), the first portion being in the semiconductor layer (portion of CH2 is in 13) and surrounded by the semiconductor layer along the second direction (portion of CH2 is surrounded by 13 in I direction), and the second portion (CH1) being in the multi-layer stacked structure (CH1 is in ST), and wherein, along the second direction (I direction), the first portion comprises a semiconductor channel layer (25, second channel layer of semiconductor material, Para [0027]) and a channel film (26, gate insulating film, Para [0027]), and the first portion has a smaller critical dimension than the second portion (CH2 has a smaller width than CH1 in I direction).
Claim 28, Choi discloses (Figs. 1 and 2C) the method of claim 27, wherein each particular one of the plurality of channel structures (CH) comprises a corresponding first portion (CH2), wherein the corresponding first portion of each particular one of the plurality of channel structures is disposed at a corresponding first end of the particular one of the plurality of channel structures (each corresponding CH2 is disposed at a corresponding end1 of CH) and is surrounded laterally by the semiconductor layer (part of CH2 is surrounded by 13), wherein the corresponding first portion of each particular one of the channel structures has a smaller critical dimension than other portions of the particular one of the channel structures (each corresponding CH2 has a smaller width than a corresponding CH1).
Claim 30, Choi discloses (Figs. 1 and 2C) the method of claim 27, wherein each of the plurality of channel structures (CH) comprises a respective dielectric filler layer (17, first insulating core, Para [0036]), a respective semiconductor channel layer (15, first channel layer may be semiconductor, Para [0026]), and a respective channel film (16, memory layer, Para [0026]), and the respective channel film (16) comprises a tunneling layer (16C, tunnel insulating layer, Para [0036]), a storage layer (16B, data storage layer, Para [0036]), and a blocking layer (16A, blocking layer, Para [0036]). Claim 31, Choi discloses (Figs. 1 and 2C) the method of claim 30, wherein a top surface of the respective dielectric filler layer (17) of each of the plurality of channel structures (CH) is below a top surface of the respective semiconductor channel layer (15) and the respective channel film (16) of each of the plurality of channel structures (top surface of 17 is below top surfaces of 15 and 16).
Claim 32, Choi discloses (Figs. 1 and 2C) the method of claim 27, wherein a dielectric sealing structure (27, second insulating core, Para [0027]) is disposed within each of the plurality of channel structures (27 is disposed within CH) at the first end of each of the plurality of channel structures (27 is within end1), and wherein a respective second semiconductor plug (CP, contact pad which may be polysilicon, Para [0028]) is disposed over the dielectric sealing structure in each of the plurality of channel structures (CP is disposed over each 27 in each CH).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15, 21, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0102372) as applied to claims 13, 19, and 27 above, and further in view of Zhang (US Pat. No. 11,158,622). Claim 15, Choi discloses the 3D memory device of claim 13. Choi does not explicitly disclose wherein the 3D memory device further comprises a plurality of first semiconductor plugs disposed at second ends of the plurality of channel structures. However, Zhang disclose (Figs. 3F-3M) a plurality of first semiconductor plugs (Fig. 3F, 344, channel local contacts, Col. 30, lines: 1-13) disposed at second ends (Fig. 3G, 344 are disposed on bottom ends of each 314, hereinafter “end2”) of a plurality of channel structures (314, channel structures, Col. 30, lines: 27-40). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the semiconductor plugs of Zhang to the memory device of Choi as the plugs allow for local and periphery connections (Zhang, Col. 30, lines: 1-13).
Claim 21, Choi discloses the system of claim 19. Choi does not explicitly disclose wherein the 3D memory device further comprises a plurality of first semiconductor plugs disposed at second ends of the plurality of channel structures. However, Zhang disclose (Figs. 3F-3M) a plurality of first semiconductor plugs (Fig. 3F, 344, channel local contacts, Col. 30, lines: 1-13) disposed at second ends (Fig. 3G, 344 are disposed on bottom ends of each 314, hereinafter “end2”) of a plurality of channel structures (314, channel structures, Col. 30, lines: 27-40). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the semiconductor plugs of Zhang to the system of Choi as the plugs allow for local and periphery connections (Zhang, Col. 30, lines: 1-13).
Claim 29, Choi discloses the method of claim 27. Choi does not explicitly disclose wherein the 3D memory device further comprises a plurality of first semiconductor plugs disposed at second ends of the plurality of channel structures. However, Zhang disclose (Figs. 3F-3M) a plurality of first semiconductor plugs (Fig. 3F, 344, channel local contacts, Col. 30, lines: 1-13) disposed at second ends (Fig. 3G, 344 are disposed on bottom ends of each 314, hereinafter “end2”) of a plurality of channel structures (314, channel structures, Col. 30, lines: 27-40). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the semiconductor plugs of Zhang to the method of Choi as the plugs allow for local and periphery connections (Zhang, Col. 30, lines: 1-13).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (US 2022/0020760) discloses (Fig. 1) a channel structure 165 comprising a first portion with critical dimension CD3 smaller than a second portion with critical dimension CD2. However, Wang does not disclose where the first portion is inside a semiconductor layer and also includes a channel film.
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