DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I in the reply filed on 02/25/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 6, 8-16, and 18-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II-IX, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/25/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “when viewed from a direction orthogonal to the main surface, the insulating layer is inside of an outer edge of the main surface” in claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakanuma et al. [JP 49-039555 B] (as cited by applicant).
Regarding Claim 1, Nakanuma et al. shows an inductor component (Figs. 2(A)-2(C) and teachings from Figs. 3(A)-3(B)) comprising:
a semiconductor substrate (201) including a semiconductor material (material of silicon, see English translation, Pages 4/5), the semiconductor substrate (201) having a main surface (top surface, see Fig. 2(B)); and
a first inductor wire (204) extending through the interior of the semiconductor substrate along the main surface (see Fig. 2(B), element 204 extending through the interior of element 201 along the top surface),
the first inductor wire (204) containing the semiconductor material (element 204 is a P-type inversion layer 204 which will contain material of silicon from element 201 and functions as an inductor as shown in Figs. 2(A)-2(C), see English translation, Pages 2/5, 3/5), and
the first inductor wire (204) having an electrical resistance lower than that of the semiconductor substrate (201, element 204 have high conductivity and element 201 made of silicon inherently have high resistance and since electrical resistance is inversely proportional to conductivity, element 204 will have an electrical resistance lower than element 201, see English translation, Pages 3/5) and being integrated with the semiconductor substrate (see Fig. 2(B), element 204 integrated with element 201).
Regarding Claim 2, Nakanuma et al. shows an insulating layer (205) on the main surface (see Fig. 2(B)).
Regarding Claim 4, Nakanuma et al. shows an external terminal (209) electrically connected to the first inductor wire (204, see Figs. 2(A)-2(B)), wherein the external terminal (209) has a terminal main surface (bottom or top surface) parallel to the main surface (element 209 has a bottom or top surface parallel to the top surface).
Regarding Claim 5, Nakanuma et al. shows when viewed from a direction orthogonal to the main surface, the external terminal (209) is inside of an outer edge of the main surface (see Fig. 2(A), when viewed from a direction orthogonal to the main surface, element 209 is inside of an outer edge of the top surface).
Regarding Claim 7, Nakanuma et al. shows a first connecting wire (element 202 or portion of element 209 at element 205, 208) including a metal material (see English translation), the first connecting wire extending in a direction orthogonal to the main surface, to connect the external terminal and the first inductor wire (see Figs. 2(A)-2(B), element 202 or portion of element 209 at element 205, 208 extending in a direction orthogonal to the main surface orthogonal to the top surface, to connect to top portion of element 209 and element 204).
Regarding Claim 17, Nakanuma et al. shows the first inductor wire (204) extends in a spiral shape (see Fig. 2(A), see English translation).
Regarding Claim 20, Nakanuma et al. shows an external terminal (209) electrically connected to the first inductor wire (204, see Figs. 2(A)-2(B)), wherein the external terminal (209) has a terminal main surface (bottom or top surface) parallel to the main surface (element 209 has a bottom or top surface parallel to the top surface).
Claim(s) 1-5, 7, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimoichi [U.S. Pub. No. 2018/0082775].
Regarding Claim 1, Shimoichi shows an inductor component (Figs. 1-5B) comprising:
a semiconductor substrate (10) including a semiconductor material (material of silicon, Paragraph [0192]), the semiconductor substrate (10) having a main surface (top surface, see Figs. 3-4); and
a first inductor wire (33) extending through the interior of the semiconductor substrate along the main surface (see Figs. 3-4, element 33 extending through the interior of element 10 along the top surface),
the first inductor wire (33) containing the semiconductor material (element 33 contain material of silicon, Paragraphs [0078], [0080]), and
the first inductor wire (33) having an electrical resistance lower than that of the semiconductor substrate (10, element 33 have conductivity and element 10 made of silicon inherently have high resistance and since electrical resistance is inversely proportional to conductivity, element 33 will have an electrical resistance lower than element 10, Paragraphs [0078], [0080], [0192]) and being integrated with the semiconductor substrate (see Figs. 3-4, element 33 integrated with element 10).
Regarding Claim 2, Shimoichi shows an insulating layer (13) on the main surface (see Figs. 3-4).
Regarding Claim 3, Shimoichi shows when viewed from a direction orthogonal to the main surface (top surface of element 10), the insulating layer (13) is inside of an outer edge of the main surface (see Figs. 1-4, when viewed from a direction orthogonal to the top surface, element 13 is inside of an outer edge of the top surface, Paragraph [0086]).
Regarding Claim 4, Shimoichi shows an external terminal (element 55 or top portion of element 54) electrically connected to the first inductor wire (33), wherein the external terminal (element 55 or top portion of element 54) has a terminal main surface (bottom or top surface) parallel to the main surface (element 55 or top portion of element 54 has a bottom or top surface parallel to the top surface).
Regarding Claim 5, Shimoichi shows when viewed from a direction orthogonal to the main surface, the external terminal (element 55 or top portion of element 54) is inside of an outer edge of the main surface (see Figs. 1-5B, when viewed from a direction orthogonal to the main surface, element 55 or top portion of element 54 is inside of an outer edge of the top surface).
Regarding Claim 7, Shimoichi shows a first connecting wire (element 54 at element 51) including a metal material (Paragraph [0095]), the first connecting wire extending in a direction orthogonal to the main surface (top surface of element 10), to connect the external terminal and the first inductor wire (see Figs. 1-4, element 54 at element 51 extending in a direction orthogonal to the top surface, to connect to element 55 and element 32, 33).
Regarding Claim 17, Shimoichi shows the first inductor wire (element 33 is part of element 11) extends in a spiral shape (see Fig. 2, Paragraph [0048]).
Regarding Claim 20, Shimoichi shows an external terminal (element 55 or top portion of element 54) electrically connected to the first inductor wire (33), wherein the external terminal (element 55 or top portion of element 54) has a terminal main surface (bottom or top surface) parallel to the main surface (element 55 or top portion of element 54 has a bottom or top surface parallel to the top surface).
Claim(s) 1-2, 4-5, 7, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanematsu [JP 2003-179146].
Regarding Claim 1, Kanematsu shows an inductor component (Figs. 1-9) comprising:
a semiconductor substrate (1) including a semiconductor material (material of silicon, Paragraph [0023]), the semiconductor substrate (1) having a main surface (top surface, see Fig. 1); and
a first inductor wire (5) extending through the interior of the semiconductor substrate along the main surface (see Figs. 1, element 5 extending through the interior of element 1 along the top surface),
the first inductor wire (5) containing the semiconductor material (element 5 is a P type diffusion layer 5 which will contain material of silicon from element 1 and functions as an inductor as shown in Fig. 1, Paragraph [0023]), and
the first inductor wire (5) having an electrical resistance lower than that of the semiconductor substrate (1, element 5 have conductivity and element 1 made of silicon inherently have high resistance and since electrical resistance is inversely proportional to conductivity, element 5 will have an electrical resistance lower than element 1, Paragraph [0023]-[0026]) and being integrated with the semiconductor substrate (see Fig. 1, element 5 integrated with element 1).
Regarding Claim 2, Kanematsu shows an insulating layer (7) on the main surface (see Fig. 1).
Regarding Claim 4, Kanematsu shows an external terminal (11) electrically connected to the first inductor wire (5, see Fig. 1), wherein the external terminal (11) has a terminal main surface (bottom or top surface) parallel to the main surface (element 11 has a bottom or top surface parallel to the top surface).
Regarding Claim 5, Kanematsu shows when viewed from a direction orthogonal to the main surface, the external terminal (11) is inside of an outer edge of the main surface (see Fig. 1, when viewed from a direction orthogonal to the main surface, element 11 is inside of an outer edge of the top surface).
Regarding Claim 7, Kanematsu shows a first connecting wire (electrode for element 21) including a metal material (Paragraph [0029]), the first connecting wire extending in a direction orthogonal to the main surface (top surface of element 1), to connect the external terminal and the first inductor wire (see Figs. 1-9, electrode for element 21 extending in a direction orthogonal to the top surface, to connect to element 11 and element 5).
Regarding Claim 17, Kanematsu shows the first inductor wire (5) extends in a spiral shape (see Fig. 1, Paragraph [0023]).
Regarding Claim 20, Kanematsu shows an external terminal (11) electrically connected to the first inductor wire (5, see Fig. 1), wherein the external terminal (11) has a terminal main surface (bottom or top surface) parallel to the main surface (element 11 has a bottom or top surface parallel to the top surface).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakanuma et al. OR Kanematsu in view of Shimoichi [U.S. Pub. No. 2018/0082775].
Regarding Claim 3, Nakanuma et al. OR Kanematsu shows the claimed invention as applied above but does not show when viewed from a direction orthogonal to the main surface, the insulating layer is inside of an outer edge of the main surface.
Shimoichi shows an inductor (Figs. 1-4) teaching and suggesting when viewed from a direction orthogonal to the main surface (top surface of element 10), the insulating layer (13) is inside of an outer edge of the main surface (see Figs. 1-4, when viewed from a direction orthogonal to the top surface, element 13 is inside of an outer edge of the top surface, Paragraph [0086]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have when viewed from a direction orthogonal to the main surface, the insulating layer is inside of an outer edge of the main surface as taught by Shimoichi for the inductor component as disclosed by Nakanuma et al. OR Kanematsu to have a compact design to reduce manufacture size, weight, and cost while facilitating insulation and improving Q-value (Paragraph [0021]).
Regarding Claim 7, Nakanuma et al. OR Kanematsu shows the claimed invention as applied above.
In addition, Shimoichi shows an inductor (Figs. 1-4) teaching and suggesting a first connecting wire (element 54 at element 51) including a metal material (Paragraph [0095]), the first connecting wire extending in a direction orthogonal to the main surface (top surface of element 10), to connect the external terminal and the first inductor wire (see Figs. 1-4, element 54 at element 51 extending in a direction orthogonal to the top surface, to connect to element 55 and element 32, 33).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a first connecting wire including a metal material, the first connecting wire extending in a direction orthogonal to the main surface, to connect the external terminal and the first inductor wire as taught by Shimoichi for the inductor component as disclosed by Nakanuma et al. OR Kanematsu to facilitate electrical connection to an external circuit to achieve desirable operating characteristics and Q-value (Paragraph [0033]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakanuma et al. OR Kanematsu in view of Kobayashi et al. [U.S. Pub. No. 2007/0013062].
Regarding Claim 3, Nakanuma et al. OR Kanematsu shows the claimed invention as applied above but does not show when viewed from a direction orthogonal to the main surface, the insulating layer is inside of an outer edge of the main surface.
Kobayashi et al. shows an inductor (Figs. 1-2) teaching and suggesting when viewed from a direction orthogonal to the main surface (top surface of element 10), the insulating layer (22) is inside of an outer edge of the main surface (see Figs. 1-2, when viewed from a direction orthogonal to the top surface, element 22 is inside of an outer edge of the top surface).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have when viewed from a direction orthogonal to the main surface, the insulating layer is inside of an outer edge of the main surface as taught by Kobayashi et al. for the inductor component as disclosed by Nakanuma et al. OR Kanematsu to have a compact design to reduce manufacture size, weight, and cost while facilitating insulation to reduce dielectric loss, increase Q-value, and functions as a stress-relaxation layer and reduces the force acting on the inductor (Paragraphs [0037], [0043]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakanuma et al. in view of Kanematsu [JP 2003-179146].
Regarding Claim 7, Nakanuma et al. shows the claimed invention as applied above.
In addition, Kanematsu shows an inductor element (Figs. 1-9) teaching and suggesting a first connecting wire (electrode for element 21) including a metal material (Paragraph [0029]), the first connecting wire extending in a direction orthogonal to the main surface (top surface of element 1), to connect the external terminal and the first inductor wire (see Figs. 1-9, electrode for element 21 extending in a direction orthogonal to the top surface, to connect to element 11 and element 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a first connecting wire including a metal material, the first connecting wire extending in a direction orthogonal to the main surface, to connect the external terminal and the first inductor wire as taught by Kanematsu for the inductor component as disclosed by Nakanuma et al. to facilitate electrical connection to an external circuit to achieve desirable operating characteristics and inductance (Paragraph [0008]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZFUNG J CHAN whose telephone number is (571)270-7981. The examiner can normally be reached M-TH 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shawki Ismail can be reached at (571)272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837
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