Prosecution Insights
Last updated: August 18, 2026
Application No. 18/296,329

SEMICONDUCTOR DEVICE WITH DEEP SILICIDE FILM

Non-Final OA §102§103
Filed
Apr 05, 2023
Priority
Jun 07, 2022 — RE 10-2022-0068662
Examiner
RODRIGUEZ VILLANU, SANDRA MILENA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
102 granted / 116 resolved
+19.9% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
42 currently pending
Career history
158
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
48.3%
+8.3% vs TC avg
§102
22.8%
-17.2% vs TC avg
§112
26.8%
-13.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 116 resolved cases

Office Action

§102 §103
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/30/2026 has been entered. Response to Amendment The Amendment filed on 06/01/2026 has been entered. Claims 2-6 and 9-10, 12-20 are withdrawn, non-elected without traverse. Claims 1-20 are pending. Response to Arguments Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the "Amendment/Req. Reconsideration-After Non-Final Reject" filed on 06/01/2026, have been fully considered, the arguments are not persuasive and some of them are moot because do not apply to new ground of rejections with a new reference, US 20220344464 A1 to Chiu, being used in the current rejection, see detail below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 1, 7 and 11 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Chiu et al. (US 20220344464 A1, hereinafter Chiu). Re: Independent Claim 1, Chiu teaches a semiconductor device (Fig. 1B), comprising: PNG media_image1.png 868 594 media_image1.png Greyscale Chiu’s Figure 1B-Annotated. a substrate (142A back-side ILD layer in [0049], Fig. 1B); an active pattern (122 channel layers in [0028], Fig. 1B) disposed on the substrate (142A) and extending in a first direction (x-direction, Fig. 1B); a plurality of gate structures (112N1-112N3 plurality of gate structure in [0024], Fig. 1B), wherein the plurality of gate structures (112N1-112N3) is disposed on the active pattern (122) and arranged in the first direction (x-direction), wherein each gate structure of the plurality of gate structures (112N1-112N3) includes a gate electrode (112B conductive layer in [0030], Fig. 1B) and a gate insulating film (112A gate dielectric layer in [0030], Fig. 1B), and wherein the gate electrode (112B) extends in a second direction (y-direction, Fig. 1B) that intersects the first direction (x-direction); a source/drain pattern (110N1-110N3 source/drain regions in [0031], Fig. 1B) disposed between adjacent gate structures of the plurality of gate structures (112N1-112N3); a source/drain contact (131B-131C metal liner 131B and contact plugs 131Cin [0033], Fig. 1B) connected (Fig. 1B) to the source/drain pattern (110N1-110N3); and a contact silicide film (131A made of silicide in [0033], Fig. 1B) disposed between the source/drain pattern (110N1-110N3) and the source/drain contact (131B-131C), wherein the contact silicide film (131A) is spaced apart (combination of Fig. 1A including 131A from Fig. 1B) from the substrate (142A), and wherein the contact silicide film (131A) includes a bowl region (bowl region 131A Fig. 1B -Annotated) that wraps a lower portion of the source/drain contact (131B-131C) by surrounding lateral sides and a bottom surface (Fig. 1B -Annotated) of the source/drain contact (131B-131C), and a protruding region (protruding region 131A Fig. 1B -Annotated) that protrudes from the bowl region (bowl region 131A) of the contact silicide film (131A) in a third direction (z-direction, Fig. 1B), wherein the third direction (z-direction) is orthogonal to the first (y-direction) and second (x-direction) directions. Re: Claim 7, Chiu discloses the semiconductor device of claim 1, wherein the active pattern (122) includes a lower pattern (a lowest layer 122-L, Fig. 1B-Annotated) that extends in the first direction (x-direction) and a plurality of sheet patterns (top layers 122-T above the lowest layer 122-L in Fig. 1B-Annotated), wherein the plurality of sheet patterns (122-T) is arranged in the third direction (z-direction) and spaced apart (Fig. 1B-Annotated, gate structure between 122 layers) from the lower pattern (122-L) in the third direction (z-direction), wherein the gate structure (112N1-112N3) includes an inner gate structure (112N3 Fig. 1B) that includes portions disposed between the lower pattern (122-L) and a sheet pattern (122-T) of the plurality of sheets patterns (122-T), and between (Fig. 1B) adjacent sheet patterns of the plurality of sheet patterns (122-T), and wherein the inner gate structure (112N3) includes the gate electrode (112B Fig. 1B) and the gate insulating film (112A Fig. 1B). Re: Claim 11, Chiu discloses the semiconductor device of claim 1, wherein the bowl region (bowl region 131A) of the contact silicide film (131A) includes (Fig. 1B-Annotated) an inner side surface (inner-131A) and an outer side surface (outer-131A), the inner side surface (inner-131A) contacts the source/drain contact (131B-131C), the outer side surface (outer-131A) contacts the source/drain pattern (110N1-110N3), the inner side surface (inner-131A) and the outer side surface (outer-131A) each have a convex shape (Fig. 1B-Annotated) that bends towards the substrate (142A), and wherein the protruding region (protruding region 131A) of the contact silicide film (131A) protrudes (Fig. 1B-Annotated) from the outer side surface (outer-131A) of the bowl region (bowl region 131A) of the contact silicide film (131A). Claim Rejections - 35 USC § 103 The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chiu in view of Choi et al. (US 20200395445 A1, hereinafter Choi, of the record). Re: Claim 8, Chiu discloses the semiconductor device of claim 7, Chiu does not expressly disclose wherein the source/drain pattern contacts the gate insulating film of the inner gate structure. However, in the same semiconductor device field of endeavor, Choi discloses a wherein the source/drain pattern (SD source/drain regions in [0020], Fig. 2A) contacts the gate insulating film (GI gate dielectric pattern in [0065], Fig. 2A) of the inner gate structure (GI, GE gate dielectric pattern GI and gate electrode GE in [0065], Fig. 2A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Choi’s feature wherein the source/drain pattern contacts the gate insulating film of the inner gate structure to Chiu’s device to meet an increasing demand for a semiconductor device with a small pattern size and a reduced design rule, the MOS-FETs may be scaled down ([0003], Choi). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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Prosecution Timeline

Show 2 earlier events
Dec 01, 2025
Interview Requested
Dec 09, 2025
Examiner Interview Summary
Feb 06, 2026
Response Filed
Mar 30, 2026
Final Rejection mailed — §102, §103
Jun 01, 2026
Response after Non-Final Action
Jun 30, 2026
Request for Continued Examination
Jul 01, 2026
Response after Non-Final Action
Jul 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.1%)
2y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 116 resolved cases by this examiner. Grant probability derived from career allowance rate.

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