Prosecution Insights
Last updated: April 19, 2026
Application No. 18/296,440

DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN SYSTEM USING PARTITIONING AND DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN METHOD USING PARTITIONING

Non-Final OA §112
Filed
Apr 06, 2023
Examiner
LIN, ARIC
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Agilesoda Inc.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
3y 3m
To Grant
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
312 granted / 521 resolved
-8.1% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
51 currently pending
Career history
572
Total Applications
across all art units

Statute-Specific Performance

§101
18.4%
-21.6% vs TC avg
§103
43.9%
+3.9% vs TC avg
§102
12.8%
-27.2% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 521 resolved cases

Office Action

§112
DETAILED ACTION This office action is in response to Application No. 18/296,440, filed on 6 April 2023. Claims 1-16 are pending. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1 and 9 recite a partition unit that changes an existing node to a cluster node according to an assigned group in consideration of an area and a quantity of standard cells, a trade-off between an internal network and an external network, and a critical path. Claims 6, 7, 14, and 15 further recite the partitioning unit determining partition sizes and weights according to specific equations. These limitations are not adequately supported by the originally-filed disclosure. See MPEP § 2161.01(I): original claims may lack written description when the claims define the invention in functional language specifying a desired result but the specification does not sufficiently describe how the function is performed or the result is achieved. For software, this can occur when the algorithm or steps/procedure for performing the computer function are not explained at all or are not explained in sufficient detail (simply restating the function recited in the claim is not necessarily sufficient). In other words, the algorithm or steps/procedure taken to perform the function must be described with sufficient detail so that one of ordinary skill in the art would understand how the inventor intended the function to be performed … When examining computer-implemented functional claims, examiners should determine whether the specification discloses the computer and the algorithm (e.g., the necessary steps and/or flowcharts) that perform the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. It is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement (emphasis added). First, there is no disclosure of how the partitioning unit changes existing nodes to cluster nodes, let alone doing so in consideration of the specific parameters recited in the claim. The Specification provides no algorithm, steps, or other explanation for how this function is actually performed. Second, there is no disclosure of how the partitioning unit considers: 1) a quantity of standard cells; 2) trade-offs between an internal network and an external network; and 3) a critical path in performing the claimed functions. The Specification discusses the partitioning unit considering parameters for balancing partition sizes, based on a specific equation, on p. 20. In particular, the partitioning unit calculates partition size according to Equation 1, a r e a c o f f × ∑ v ∈ p A v + r o u t e c o f f × ∑ e ⊂ p n ( e ) . Equation 1 has no term for the quantity of standard cells, only the area of the standard cells. There is also no term for ‘trade-offs between an internal network and an external network’, or even any explanation of what those trade-offs are and why they are relevant to the functions of the partitioning unit. Finally, there is no term for the critical path in partition size. Third, there is no disclosure of how areacoff and routecoff are determined. These terms are necessary for determining partition size and weights, which are in turn necessary for the partitioning unit to perform its functions of partitioning and updating the hypergraph. Thus, Applicant has failed to adequately disclose how the partitioning unit functions. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 11 March 2026 /ARIC LIN/ Examiner, Art Unit 2851
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Prosecution Timeline

Apr 06, 2023
Application Filed
Mar 12, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+12.6%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 521 resolved cases by this examiner. Grant probability derived from career allow rate.

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