DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 04/06/2025 has been considered.
Drawings
The drawings filed on 04/06/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 04/06/2023 are acceptable
Claim Objections
Claim 11 is objected to because of the following informalities: there is a comma missing at the end of line 14 of the claim, between “second direction” and “upper dummy pads”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Baek (US 2009/0057880).
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Regarding claim 1, Baek (US 2009/0057880) discloses:
A stack semiconductor package (300, ¶0072) comprising:
a base chip (380, ¶0072);
at least two semiconductor chips (each semiconductor chip 310 in figure 10 has the structure of semiconductor chip 100d in figure 6, ¶0072) stacked on the base chip (380); and
a sealing material sealing (¶0078) the at least two semiconductor chips (310) on the base chip (380), wherein the at least two semiconductor chips comprise an uppermost semiconductor chip (310) and at least one first semiconductor chip (310) under the uppermost semiconductor chip, and the first semiconductor chip comprises, through electrodes (170, ¶0073) arranged in a central portion of the first semiconductor chip, the central portion of the first semiconductor chip being a portion on a plane defined by a first direction and a second direction perpendicular to the first direction, the central portion of the first semiconductor chip disposed centrally along the first direction, the through electrodes arranged along the second direction, upper dummy pads (110, ¶0073) on outer portions of a back side of the first semiconductor chip, the back side being a non-active surface of the first semiconductor chip, the outer portions being at both sides of the central portion in the first direction, and a dummy pattern (150) connecting the upper dummy pads (110) with each other on the back side of the first semiconductor chip (110).
Regarding claim 2, Baek further discloses:
wherein at least three of the upper dummy pads (110) are connected to each other through the dummy pattern (150) in at least one of the first direction and the second direction (figure 6).
Regarding claim 3, Baek further discloses:
wherein the upper dummy pads (110) are provided in two rows each arranged in the second direction, two of the upper dummy pads adjacent to each other in the first direction are connected to each other through the dummy pattern (150), and two of the upper dummy pads adjacent to each other in a first row in the second direction and two of the upper dummy pads adjacent to each other in a second row in the second direction are alternately connected to each other through the dummy pattern, along the second direction (figure 6).
Regarding claim 6, Baek further discloses:
wherein at least one of the upper dummy pads (110) is connected to one of the through electrodes (170) that is connected to ground through the dummy pattern (110).
Regarding claim 7, Baek further discloses:
wherein the first semiconductor chip further comprises:
lower dummy pads (110) on a front side, the front side being an active surface, the lower dummy pads corresponding to the upper dummy pads (110), respectively;
lower electrode pads (120, ¶0073) on the front side and connected to the through electrodes (170), respectively; and
bumps (380, figure 12) arranged on lower surfaces of the lower dummy pads and the lower electrode pads.
Regarding claim 8, Baek further discloses:
wherein upper electrode pads (120) are arranged on upper surfaces of the through electrodes (170), respectively, wherein the upper electrode pads and the upper dummy pads include a same structure (pad structure) and a same material” (conductive material, ¶0049).
Regarding claim 9, Baek further discloses:
wherein the base chip comprises (380) a package substrate (¶0072), and the at least two semiconductor chips (100, 310) comprise a master chip and one or more core chips (¶0043) .
Regarding claim 10, Baek further discloses:
wherein the base chip (380) comprises a buffer chip (¶0072), the at least two semiconductor chips (100, 310) comprise core chips (¶0043), and the base chip includes a through electrode (170).
Regarding claim 11, Baek further discloses:
A stack semiconductor package comprising:
a package substrate (380);
at least two semiconductor chips (310) stacked on the package substrate (380);
a sealing material (¶0078) sealing the at least two semiconductor chips on the package substrate; and
an external connection terminal (491, ¶0077) on a lower surface of the package substrate (380, figure 12) the at least two semiconductor chips (310) including an uppermost semiconductor chip (310) and at least one first semiconductor chip (310) under the upper semiconductor chip, the first semiconductor chip comprising, through electrodes (170) arranged in a central portion of the first semiconductor chip, the central portion of the first semiconductor chip being a portion on a plane defined by a first direction and a second direction perpendicular to the first direction, the central portion of the first semiconductor chip disposed centrally along the first direction, the through electrodes arranged along the second direction upper dummy pads (110) on outer portions of a back side of the first semiconductor chip, the back side being a non-active surface of the first semiconductor chip, the outer portions being at both sides of the central portion, respectively, in the first direction, and a dummy pattern (150) connecting the upper dummy pads with each other on the back side.
Regarding claim 12, Baek further discloses:
wherein at least three of the upper dummy pads (110) are connected to each other through the dummy pattern (150) in the first direction.
Regarding claim 13, Baek further discloses
wherein at least one of the upper dummy pads (110) is connected to one of the through electrodes (170) that is connected to ground through the dummy pattern (150).
Regarding claim 14, Baek further discloses:
wherein the first semiconductor chip further comprises:
lower dummy pads (110) on a front side, the front side being an active surface, the lower dummy pads corresponding to the upper dummy pads (110), respectively;
lower electrode pads (120) on the front side and connected to the through electrodes (170), respectively; and
bumps (380) arranged on lower surfaces of the lower dummy pads and the lower electrode pads.
Regarding claim 15, Baek further discloses:
wherein upper electrode pads (120) are arranged on upper surfaces of the through electrodes (170), respectively, and the upper electrode pads (120) and the upper dummy pads (110) include a same structure (pad structure) and a same material (conductive material, ¶0049).
Regarding claim 16, Baek further discloses:
wherein the at least two semiconductor chips comprises a master chip and one or more core chips (¶0043).
Regarding claim 17, Baek discloses:
A stack semiconductor package comprising:
a buffer chip (310) having first through electrodes (170);
at least two semiconductor chips (310) stacked on the buffer chip; and
a sealing material (¶0078) sealing the at least two semiconductor chips on the buffer chip, wherein the at least two semiconductor chips comprise an uppermost semiconductor chip and at least one first semiconductor chip under the uppermost semiconductor chip, the first semiconductor chip comprising, second through electrodes (170) arranged in a central portion of the first semiconductor chip, the central portion of the first semiconductor chip being a portion on a plane defined by a first direction and a second direction perpendicular to the first direction, the central portion of the first semiconductor chip disposed centrally along the first direction, the second through electrodes arranged along the second direction, upper dummy pads (110) on outer portions of a back side of the first semiconductor chip, the back side being a non-active surface of the first semiconductor chip, the outer portions being at both sides of the central portion, respectively, in the first direction, and a dummy pattern (150) connecting the upper dummy pads with each other on the back side.
Regarding claim 18, Baek further discloses:
wherein at least three of the upper dummy pads (110) are connected to each other through the dummy pattern (150) in at least one of the first and the second direction.
Regarding claim 19, Baek further discloses:
wherein at least one of the upper dummy pads (110) is connected to one of the second through electrodes (170) that is connected to ground through the dummy pattern (120).
Regarding claim 20, Baek further discloses:
wherein the first semiconductor chip further comprises:
lower dummy pads (110) on a front side, is the front side being an active surface, the lower dummy pads (110) corresponding to the upper dummy pads (110), respectively;
lower electrode pads (120) on the front side and connected to the second through electrodes (170), respectively; and
bumps (380) arranged on lower surface of the lower dummy pads and the lower electrode pads, and the lower electrode pads include a same structure and a same material as the lower dummy pads (¶0043).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek.
Regarding claim 4, Baek does not disclose “wherein the upper dummy pads (110) include first upper dummy pads arranged at four vertices of a rectangle and a second upper dummy pad arranged at a center of the rectangle, and the second upper dummy pad is connected to each of the first upper dummy pads through the dummy pattern in the diagonal direction”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 5, Baek does not disclose “wherein the rectangle is repeatedly arranged in the second direction, at least a pair of the first upper dummy pads adjacent to each other in the second direction is connected to each other through the dummy pattern, and the second upper dummy pad and another second upper dummy pad adjacent to the second upper dummy pad in the second direction are connected to each other through the dummy pattern. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899