DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 10-11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (PG Pub. No. US 2021/0249516 A1) in view of Yang et al. (PG Pub. No. US 2023/0061138 A1).
Regarding claim 1, Li teaches a semiconductor device (¶ 0020: 10 and/or 100) comprising:
a semiconductor layer (¶ 0026: 102) including first conductivity-type impurities (¶ 0026: p-type);
first active structures (¶ 0015: 212/214) extending upwardly from the semiconductor layer (fig. 15: 212/214 extend indirectly from 102) and including the first conductivity-type impurities (¶ 0017: 214 comprises p-type dopant);
a first well region (¶ 0022: 104) in the semiconductor layer (fig. 15: 104 disposed in 102), wherein the first well region includes second conductivity-type impurities (¶ 0027: p-type well);
second active structures (¶ 0015: 208/210) extending upwardly from the first well region, between the first active structures in a first direction (figs. 9, 15: 208/210 extend upward from 104 between 212/214 in C-C cutline direction), wherein the second active structures include the second conductivity-type impurities (¶ 0017: 208/210 includes n-type dopant);
third active structures (¶ 0015: 206) extending upwardly from the first well region, between the second active structures in the first direction (fig. 15: 206 extend upward from 104 between 208/210), wherein the third active structures include the first conductivity-type impurities (¶ 0017: 206 comprises p-type dopant); and
dummy gate structures (¶ 0070: 72) intersecting the first and second active structures on the semiconductor layer, respectively, and extending in a second direction (figs. 12, 14: patterned portions of 72 intersect 212/214 and 208/210 on 102, and extend in A-A cutline direction),
wherein at least one of the second and third active structures includes a second epitaxial layer (¶ 0039: at least one of 206, 208 and 210 formed by an epitaxial growth process) that integrates with the first well region (fig. 34 among others: 206, 208 and/or 210 integrate with 104 through regions 106/108 and/or 110).
Li further teaches the substrate comprises a semiconductor layer on an insulating layer (¶ 0023).
Li does not teach the first well region comprises a first epitaxial layer.
Yang teaches a semiconductor device (fig. 2D) including a well region (¶ 0030: 104 or 106, similar to 104 of Li) comprising an epitaxial layer (¶ 0032: well regions 104 and 106 are portions of an epitaxy layer).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the well region of Li as an epitaxial layer, as a means to provide a region with appropriate doping to form the well region of Li.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, epitaxial material is suitable to provide the well region of Li, as evidenced by Yang.
Regarding claim 2, Li in view of Yang teaches the semiconductor device of claim 1, wherein the third active structures overlap the first epitaxial layer in a third direction, perpendicular to an upper surface of the semiconductor layer (Li, 206 vertically overlaps 104, as modified by Yang to comprise epitaxial material).
Regarding claim 3, Li in view of Yang teaches the semiconductor device of claim 1, wherein, in a plan view, the second active structures at least partially surround the third active structures (Li, fig. 12 among others: 208/210 at least partially surround 206), and the first active structures at least partially surround the second active structures (Li, fig. 12 among others: 212/214 at least partially surround 208/210).
Regarding claim 4, Li in view of Yang teaches the semiconductor device of claim 1, wherein a lower surface and side surfaces of the first epitaxial layer are in contact with the semiconductor layer (Li, fig. 14: lower and side surfaces of 104, as modified by Yang to comprise epitaxial material, contact 102).
Regarding claim 5, Li in view of Yang teaches the semiconductor device of claim 1, further comprising an insulating liner layer between the first epitaxial layer and the semiconductor layer (Li, ¶ 0023: 102 comprises a semiconductor-on-insulator substrate, such that a non-illustrated insulating liner layer is disposed between well region 104, as modified by Yang to include epitaxial material, and semiconductor substrate 102).
Furthermore, the Examiner notes that the features of claim 5 (“an insulating liner layer between the epitaxial layer and the semiconductor layer”) appears to be mutually exclusive to those of claim 4 (“a lower surface and side surfaces of the epitaxial layer are in contact with the semiconductor layer”). Should applicant traverse on the grounds that the arrangement of an insulating liner layer between the epitaxial layer and the semiconductor layer is a non-obvious variant from the arrangement of the epitaxial layer in contact with the semiconductor layer, Applicant should submit evidence or identify such evidence now of record showing the inventions to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
Regarding claim 10, Li in view of Yang teaches the semiconductor device of claim 1, wherein the dummy gate structures extend to further intersect the third active structures (Li, fig. 15: portions of 72 extend to intersect 206), and the semiconductor device further comprises:
first source layers (Li, ¶ 0015: 82) on the first active structures outside the dummy gate structures (Li, fig. 14: 82 disposed on 212/214 outside patterned portions of 72), wherein the first source layers include the first conductivity-type impurities (Li, ¶ 0056: 82 comprise p-type impurities/dopant);
second source layers (Li, ¶ 0015: 84) on the second active structures outside the dummy gate structures (Li, fig. 14: 84 disposed on 212/214 outside patterned portions of 72), wherein the second source layers include the second conductivity-type impurities (Li, ¶ 0057: 208/210 comprise n-type impurities/dopant);
and third source layers (Li, ¶ 0015: 86) on the third active structures outside the dummy gate structures (Li, fig. 14: 86 disposed on 206 outside patterned portions of 72), wherein the third source layers include the first conductivity-type impurities (Li, ¶ 0056: 206 comprises p-type impurities/dopant).
Regarding claim 11, Li in view of Yang teaches the semiconductor device of claim 10, further comprising contact plugs (Li, ¶ 0078: 422/424/426/428/430) on the first to third source layers (fig. 34: 422/424/426/428/430 disposed on 82/84/86).
Regarding claim 14, Li in view of Yang teaches the semiconductor device of claim 1, wherein the dummy gate structures are spaced apart between the first active structures and the second active structures and are spaced apart between the second active structures and the third active structures, in the second direction (Li, fig. 14).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Yang as applied to claim 1 above, and further in view of Wang et al. (PG Pub. No. US 2022/0352321 A1).
Regarding claim 9, Li in view of Yang teaches the semiconductor device of claim 1, wherein the first active structures comprise first lower regions (Li, patterned fins 212/214 and/or well regions 112/114) extending from the semiconductor layer (Li, 212/214 and/or 112/114 at least indirectly extend from 104),
the second active structures comprise second lower regions (Li, patterned fins 208/210 and/or well regions 108/110) extending from the first epitaxial layer (Li, 208/210 and/or 108/110 at least indirectly extend from 104), and
the third active structures comprise third lower regions (Li, patterned fins 206 and/or well region 106) extending from the first epitaxial layer (Li, 206 and/or 106 at least indirectly extend from 104),
wherein a length from an upper surface of the semiconductor layer to upper surfaces of the first to third lower regions is about 100 nanometers (nm) to about 700 nm (Li, ¶ 0035: height of patterned fins between about 100 nm to 150 nm).
Li in view of Yang does not explicitly teach wherein a length from a lower surface of the semiconductor layer to upper surfaces of the first to third lower regions is about 100 nanometers (nm) to about 700 nm.
Wang teaches a semiconductor device (figs. 22A-22B) including a semiconductor layer (¶¶ 0020, 0025: well regions 602/604 of fins 52) and lower regions (fin portions 58), wherein a length from a lower surface of the semiconductor layer to upper surfaces of the lower regions is about 100 nanometers (nm) to about 700 nm (¶ 0066: well region extends 20 nm to 600 nm below fin portion 58).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the depth of the semiconductor layer of Li in view of Yang, as a means to optimize the doping concentration in the semiconductor layer to reduce well resistance and isolation leakage current (Wang, ¶ 0021).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of about 100 nanometers to about 700 nm at least overlaps the ranges disclosed by Li and Wang.
Claim(s) 15-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Yang and Cho et al. (PG Pub. No. US 2021/0305130 A1).
Regarding claim 15, Li teaches a semiconductor device comprising:
a first device including a semiconductor layer (104/108/110) including first conductivity-type impurities (¶¶ 0017, 0022: 104/106/108 includes at least one conductivity type impurity), first active structures (¶ 0015: 208) extending in a first direction on the semiconductor layer and including the first conductivity-type impurities (figs. 6, 9: 208 extends in first direction on 104/108/110 and includes same impurity type as 108), a first well region (¶ 0017: 106) in the semiconductor layer (fig. 4: 106 disposed in layer comprising 108/110), wherein the first well region includes second conductivity-type impurities (¶ 0017), second active structures (¶ 0015: 206) extending in the first direction on the first well region (figs. 6, 9: 206 extends in first direction on 106) and including the second conductivity-type impurities (¶ 0033: 206 patterned from and comprises same impurities as 106), third active structures (¶ 0033: 210) extending in the first direction on the first well region (fig. 6: 210 extends in first direction at least indirectly on 106) and including the first conductivity-type impurities (¶¶ 0017, 0033: 210 includes first impurity type of 110), and a dummy gate structure (¶ 0070: 72) extending in a second direction on the semiconductor layer (fig. 12: portions of 72 extend across 206/208/210), wherein at least one of the second and third active structures includes a second epitaxial layer (¶ 0039: at least one of 206, 208 and 210 formed by an epitaxial growth process) that integrates with the first well region (fig. 34 among others: 206, 208 and/or 210 integrate with 106); and
a second device (figs. 14, 33-35: at least one second device) including an active region extending in the first direction (206, 208, 210, 212 and/or 214 of second device extend in C-C and D-D cutline direction), a gate structure (¶ 0046: 72) intersecting the active region on the active region and extending in the second direction (figs. 12, 14 among others: 72 intersects 206, 208, 210, 212 and/or 214 of second device and extends in A-A and B-B cutline direction), source layers (¶0015: 82/84/86) on both sides of the gate structure (fig. 14 among others).
Li does not teach the first well region comprises a first epitaxial layer, or the semiconductor device comprises a buried interconnection line below the source layers and electrically connected to at least a portion of the source layers.
Yang teaches a semiconductor device (fig. 2D) including a well region (¶ 0030: 104 or 106, similar to 106 of Li) comprising an epitaxial layer (¶ 0032: well regions 104 and 106 are portions of an epitaxy layer).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the well region of Li as an epitaxial layer, as a means to provide a region with appropriate doping to form the well region of Li.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, epitaxial material is suitable to provide the well region of Li, as evidenced by Yang.
Li in view of Yang does not teach the semiconductor device comprises a buried interconnection line below the source layers and electrically connected to at least a portion of the source layers.
Cho teaches a semiconductor device (fig. 14 among others) including a buried interconnection line (¶ 0110: LWL) below a plurality of source layers (¶ 0071: 156a, 156b) and electrically connected to at least a portion of the source layers (fig. 14: LWL disposed below and electrically connected to 156a/156b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Li in view of Yang with the buried interconnection line of Cho, as a means to provide power to device regions (Cho, ¶ 0071), allowing for highly integrated circuit semiconductor devices (Cho, ¶ 0003).
Regarding claim 16, Li in view of Yang and Cho teaches the semiconductor device of claim15, wherein the first device further comprises interconnection lines (Li, ¶¶ 0078-0079: 422, 424, 426, 428, 430, 512, 514, 516, 518, and/or 520) electrically connected to the semiconductor layer, the first epitaxial layer, and the third active structures (Li, fig. 38: 422, 424, 426, 428, 430, 512, 514, 516, 518, and/or 520 electrically connected to 102/104/106/206), and spaced apart from each other on the dummy gate structure (Li, fig. 37: at least 422, 424, 426, 428 and 430 laterally spaced apart on 310/320/33/340).
Regarding claim 18, Li in view of Yang and Cho teaches the semiconductor device of claim 15, wherein the second device further comprises the semiconductor layer extending below the active region from the first device (Liu, fig. 15: device comprising 208/210 comprises 102 extending below 108/208 from device comprising 112/212),
wherein the buried interconnection line is below the semiconductor layer (Cho, fig. 14: LWL disposed below 150, corresponding to 102 of Li).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Yang and Cho as applied to claim 15 above, and further in view of Frougier et al. (PG Pub. No. US 2020/0287046 A1).
Regarding claim 17, Li in view of Yang and Cho teaches the semiconductor device of claim 15, wherein the second device further comprises a plurality of channel layers (Li, ¶ 0046: channel regions of fins 208) on the active region (¶ 0046 & fig. 15: channel regions of 208 disposed on non-channel portions of 208/108).
Li in view of Yang and Cho does not teach the channel layers are spaced apart from each other in a third direction, perpendicular to an upper surface of the active region, and surrounded by the gate structure.
Frougier teaches a semiconductor device (100) including channel layers (¶ 0043: 124, 126 and 128) spaced apart from each other in a third direction, perpendicular to an upper surface of an active region, and surrounded by a gate structure (fig. 5: 124/126/128 spaced apart in the vertical direction perpendicular to surface of substrate 102, and surrounded by gate 130/132).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the channel layers of Li in view of Yang and Cho as spaced apart channel layers, as a means to provide improved control of channel current flow, fuller depletion in the nanosheet channel regions and reduced short-channel effects (Frougier, ¶ 0002).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Hu et al. (PG Pub. No. US 2013/0328162 A1) and Yang.
Regarding claim 19, Li teaches a semiconductor device (figs. 14-15 among others) comprising:
a first semiconductor region (¶¶ 0015, 0017: region 12, including 112/212 and/or 102) including a semiconductor layer including first conductivity-type impurities (¶ 0026: p-type semiconductor material of substrate 102) and first active structures (¶ 0015: 112/212 includes active fin patterns) on the semiconductor layer (figs. 14-15: 112/212 disposed on 102);
a second semiconductor region (¶¶ 0015, 0017: region 14, including 108/208 and/or 104) including a well region in the semiconductor layer (figs. 14-15: 104 and/or 108 includes a well region in 102), wherein the well region includes second conductivity-type impurities (¶¶ 0017, 0022: 104/108 includes n-type impurities/dopant) and second active structures (¶ 0015: 208) on the well region (figs. 14-15: 208 disposed on 104/108); and
a third semiconductor region (¶¶ 0015, 0017: region of 14 overlapping 12, including 106/206) including third active structures (¶ 0015: 206) on the well region (figs. 14-15: 206 disposed on 104), wherein the third active structures extend upwardly from the well region (fig. 6: 206 extend upwardly away from 104) and include the first conductivity-type impurities (¶ 0017: 206 comprises p-type impurities/dopant),
wherein the third active structures include a lower region integrating with the well region (fig. 6 among others: 106 and/or lower portion of 206 integrates with 104) and an upper region (206 and/or 206a) including the first conductivity-type impurities on the lower region (¶ 0017: 206/206a includes p-type impurities/dopant disposed on lower portion of 206 and/or 106).
Li further teaches the substrate comprises a semiconductor layer on an insulating layer (¶ 0023).
Li does not teach the well region comprises an epitaxial layer, or the lower region of the third active structures integrating with the epitaxial layer as a single epitaxial layer and including the second conductivity-type impurities.
Hu teaches a semiconductor device (¶ 0016: 100) including an upper active region (¶ 0016: 104 and/or 109, similar to 206 of Li) integrating with a well region (¶ 0018: 107A and/or 107B, similar to 106 and/or 104 of Li) as a single layer (fig. 1B: 109 formed from layer including 107A/107B) and including first conductivity-type impurities (¶ 0018: 109 includes n-type impurities/dopant), the well region including second conductivity-type impurities (¶ 0018: 107B includes p-type impurities/dopant).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the lower region of the third active structures of Li to include the integration and conductivity-types of Hu (opposite to upper/channel region impurities), as a means to prevent punch-through during operation which would disable the device (Hu, ¶ 0019).
Li in view of Hu does not teach the well region comprises an epitaxial layer.
Yang teaches a semiconductor device (fig. 2D) including a well region (¶ 0030: 104 or 106, similar to 104 of Li and/or 107A/107B of Hu) comprising an epitaxial layer (¶ 0032: well regions 104 and 106 are portions of an epitaxy layer).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the well region of Li in view of Hu as an epitaxial layer, as a means to provide a region with appropriate doping to form the well regions of Li and/or Hu.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, epitaxial material is suitable to provide the well region of Li, as evidenced by Yang.
Regarding claim 20, Li in view of Hu and Yang teaches the semiconductor device of claim 19, wherein the second active structures integrate with the epitaxial layer as a single layer (Li, figs. 14-15: 208 integrates with 108/104, as modified by Yang to include epitaxial material) and include the second conductivity-type impurities (Li, ¶ 0017: 108 includes n-type impurity/dopant).
Allowable Subject Matter
Claims 6-8 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations stating:
“a dummy active structure between the second active structures and the third active structures in the first direction, wherein the dummy active structure includes a first region including the first conductivity-type impurities and a second region including the second conductivity-type impurities” as recited in claim 6, and
“a dummy active structure between the first active structures and the second active structures, wherein the dummy active structure includes a first region including the second conductivity-type impurities and a second region including dummy channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the semiconductor layer” as recited in claim 12.
Claims 7-8 and 13 depend on claims 6 and 12, and are allowable for implicitly including the allowable subject matter above.
Response to Arguments
Applicant’s arguments with respect to the 35 USC § 103 rejections of claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/Examiner, Art Unit 2818