DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 9-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2015/0262900 A1 hereinafter referred to as "Wang").
With respect to claim 1, Wang discloses, in Figs.2-8, a semiconductor device comprising: a
substrate (10) comprising a first top surface and a first bottom surface, the first top surface comprising a
first plurality of electrical contacts (710) (see Par.[0027] wherein FIG. 7 is a sectional view of an
implementation of the apparatus 100 shown in FIG. 3 in which conductive members 710 are formed in
and/or on the surface of the first side 12 of the first substrate 10); a first plurality of electrical connections
(40) directly coupled to the first plurality of electrical contacts (710) (see Par.[0026] wherein FIG. 4 is a plan view of the apparatus 100 shown in FIGS. 1-3, illustrating that the dam structure 60 may comprise a
continuous barrier extending around the IC memory chip 30 and the plurality of first conductive members
40 (which are obstructed from view in FIG. 4)); a circuit (30) comprising a second top surface and a
second bottom surface, the second bottom surface comprising a second plurality of electrical contacts,
the second plurality of electrical contacts being directly coupled to the first plurality of electrical
connections (40), the circuit further comprising a first side surface and a second side surface (see
Par.[0015] wherein the dam structure 60 prevents the first underfill material 110 from spreading further
inward towards the IC memory chip 30, and may thus aid in ensuring that a portion of the surface on the
first side 12 of the first substrate 10 will be free of underfill material and/or otherwise available to receive
and adequately adhere to the first TIM member 80 and/or the lid 70); a ring structure (60) coupled to the
substrate and positioned around the circuit, the ring structure comprising a third top surface, a height
difference between the second top surface and the third top surface being less than 100µm (see
Par.[0021]-[0024] wherein the dam structure 60 may comprise one or more layers of conductive and/or
dielectric materials, such as copper, aluminum, doped polysilicon, titanium, titanium nitride, tantalum
nitride, titanium, silicon nitride, silicon oxide, combinations and/or alloys thereof, and/or other materials,
and may be formed utilizing chemical-vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal
organic CVD (MOCVD), sputtering, epitaxial growth, and/or other processes; see Par.[0052] wherein the
dam structure may comprise a member having a width and a height, wherein the member extends around
a substantial portion of the plurality of first conductive members; in some embodiments, the width may be
about 20 microns and the height may be about 12 microns (i.e.; < 100 microns); see [0022] wherein
he dam structure 60 may be or comprise one or more members each having a width W and a thickness T;
the width W may range between about five microns and about forty microns, such as in implementations
in which the width W is about twenty microns, although other dimensions are also within the scope of the
present disclosure; the thickness T may range between about four microns and about twenty microns,
such as in implementations in which the thickness T is about twelve microns, although other dimensions
are also within the scope of the present disclosure); and a filling material (120) comprising a first portion
and a second portion, the first portion being directly coupled to the first plurality of electrical connections
(40) and the second bottom surface, the second portion being in direct contact with the first side surface, the filling material (120) being positioned between the circuit (30) and the ring structure (60), the filling material being thermally conductive and comprising a thermosetting epoxy resin (see
Par.[0018]-[0020] wherein the first underfill material 110 and/or the second underfill material 120 may be
or comprise various types of underfill polymers, such as may comprise epoxy (i.e.; epoxy is a type of thermosetting polymer), silicone, phosphine oxide, polyethylene/polypropylene copolymers, and/or urethane polymers, including resin transfer molding (low pressure) and injection transfer molding (high pressure), among other examples).
With respect to claim 2, Wang discloses, in Figs.2-8, the semiconductor device, further
comprising a second plurality of electrical connections directly coupled to the first bottom surface.
With respect to claim 3, Wang discloses, in Figs.2-8, the semiconductor device, wherein: the
second portion comprises a third side surface and a fourth side surface; the third side surface is in direct
contact with the first side surface; and the fourth side surface is in direct contact with the ring structure
(60).
With respect to claim 4, Wang discloses, in Figs.2-8, the semiconductor device, wherein, the
height difference is no greater than 50µm (see Par.[0052] wherein the dam structure may comprise a
member having a width and a height, wherein the member extends around a substantial portion of the
plurality of first conductive members; in some embodiments, the width may be about 20 microns and the
height may be about 12 microns (i.e.; < 100 microns); see Par.[0022] wherein he dam structure 60 may
be or comprise one or more members each having a width W and a thickness T; the width W may range
between about five microns and about forty microns, such as in implementations in which the width W is
about twenty microns, although other dimensions are also within the scope of the present disclosure; the
thickness T may range between about four microns and about twenty microns, such as in
implementations in which the thickness T is about twelve microns, although other dimensions are also
within the scope of the present disclosure).
With respect to claim 5, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
ring structure (60) is coupled to the substrate (20) using a glue material, an adhesive material, and/or a
thermoset epoxy material (110) (see Par.[0020] wherein the first underfill material 110 and/or the second
underfill material 120 may be or comprise various types of underfill polymers, such as may comprise
epoxy, silicone, phosphine oxide, polyethylene/polypropylene copolymers, and/or urethane polymers, including resin transfer molding (low pressure) and injection transfer molding (high pressure), among
other examples).
With respect to claim 6, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
ring structure comprises a solder mask material, a copper material, a stainless-steel material, a kovar
material, a copper tungsten material, a metal alloy material, and/or a ceramic material (see [0024]
wherein the dam structure 60 may comprise one or more layers of conductive and/or dielectric materials,
such as copper, aluminum, doped polysilicon, titanium, titanium nitride, tantalum nitride, titanium, silicon
nitride, silicon oxide, combinations and/or alloys thereof, and/or other materials, and may be formed
utilizing chemical-vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal organic CVD
(MOCVD), sputtering, epitaxial growth, and/or other processes).
With respect to claim 9, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
ring structure is characterized by a square shape, a rectangular shape, or a circular shape.
With respect to claim 10, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
first bottom surface comprises a second plurality of electrical contacts, the first plurality of electrical
contacts being coupled to the second plurality of electrical contacts.
With respect to claim 11, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
ring structure is coupled to the substrate using an epoxy material or an adhesive material (see Par.[0020]
wherein the first underfill material 110 and/or the second underfill material 120 may be or comprise
various types of underfill polymers, such as may comprise epoxy, silicone, phosphine oxide,
polyethylene/polypropylene copolymers, and/or urethane polymers, including resin transfer molding (low
pressure) and injection transfer molding (high pressure), among other examples).
With respect to claim 12, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
filling material (120) comprises an epoxy material (see Par.[0020] wherein the first underfill material 110
and/or the second underfill material 120 may be or comprise various types of underfill polymers, such as
may comprise epoxy, silicone, phosphine oxide, polyethylene/polypropylene copolymers, and/or urethane
polymers, including resin transfer molding (low pressure) and injection transfer molding (high pressure),
among other examples).
With respect to claim 13, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
filling material comprises an adhesive material (see Par.[0020] wherein the first underfill material 110
and/or the second underfill material 120 may be or comprise various types of underfill polymers, such as
may comprise epoxy, silicone, phosphine oxide, polyethylene/polypropylene copolymers, and/or urethane
polymers, including resin transfer molding (low pressure) and injection transfer molding (high pressure),
among other examples).
With respect to claim 14, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
filling material comprises a resin material (see Par.[0020] wherein the first underfill material 110 and/or
the second underfill material 120 may be or comprise various types of underfill polymers, such as may
comprise epoxy, silicone, phosphine oxide, polyethylene/polypropylene copolymers, and/or urethane
polymers, including resin transfer molding (low pressure) and injection transfer molding (high pressure),
among other examples).
With respect to claim 15, Wang discloses, in Figs.2-8, the semiconductor device, wherein the second portion comprises a third side surface, the third side surface is characterized by a curved profile.
With respect to claim 16, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
first plurality of electrical connections comprises a solder material (see Par.[0014]-[0015] wherein
common type of packaging for IC chips is the ball grid array (BGA) package, which uses multiple solder
balls or bumps for electrical and mechanical interconnection of IC chips to other devices; the plurality of
first conductive members 40 may comprise a first conductive bump (CBA) array and the plurality of
second conductive members 50 may comprise a second CBA; the first and second CBAs may each be or
comprise a ball grid array (BGA)).
With respect to claim 17, Wang discloses, in Figs.2-8, a semiconductor device comprising: a
substrate (10) comprising a first top surface and a first bottom surface, the first top surface comprising a
first plurality of electrical contacts, the first bottom surface comprising a second plurality of electrical
contacts (710), the substrate further comprising a ring structure (60) (see Par.[0027] wherein FIG. 7 is a
sectional view of an implementation of the apparatus 100 shown in FIG. 3 in which conductive members
710 are formed in and/or on the surface of the first side 12 of the first substrate 10); a first plurality of electrical connections being positioned within the ring structure (60); a second plurality of electrical
connections directly coupled to the second plurality of electrical contacts (see Par.[0026] wherein FIG. 4
is a plan view of the apparatus 100 shown in FIGS. 1-3, illustrating that the dam structure 60 may
comprise a continuous barrier extending around the IC memory chip 30 and the plurality of first
conductive members 40 (which are obstructed from view in FIG. 4); see Par.[0021]-[0024] wherein the
dam structure 60 may comprise one or more layers of conductive and/or dielectric materials, such as
copper, aluminum, doped polysilicon, titanium, titanium nitride, tantalum nitride, titanium, silicon nitride,
silicon oxide, combinations and/or alloys thereof, and/or other materials, and may be formed utilizing
chemical-vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal organic CVD (MOCVD),
sputtering, epitaxial growth, and/or other processes; see Par.[0052] wherein the dam structure may
comprise a member having a width and a height, wherein the member extends around a substantial
portion of the plurality of first conductive members; in some embodiments, the width may be about 20
microns and the height may be about 12 microns (i.e.; < 100 microns); see Par.[0022] wherein he dam
structure 60 may be or comprise one or more members each having a width W and a thickness T; the
width W may range between about five microns and about forty microns, such as in implementations in
which the width W is about twenty microns, although other dimensions are also within the scope of the
present disclosure; the thickness T may range between about four microns and about twenty microns,
such as in implementations in which the thickness T is about twelve microns, although other dimensions
are also within the scope of the present disclosure); a circuit (30) comprising a second top surface and a
second bottom surface, the second bottom surface comprising a second plurality of electrical contacts,
the second plurality of electrical contacts being directly coupled to the first plurality of electrical
connections, the circuit further comprising a first side surface and a second side surface (see Par.[0015]
wherein the dam structure 60 prevents the first underfill material 110 from spreading further inward
towards the IC memory chip 30, and may thus aid in ensuring that a portion of the surface on the first side
12 of the first substrate 10 will be free of underfill material and/or otherwise available to receive and
adequately adhere to the first TIM member 80 and/or the lid 70); and a filling material (120) comprising a
first portion and a second portion, the first portion being directly coupled to the first plurality of electrical
connections and the second bottom surface, the second portion being in direct contact with the first side surface and the ring structure, the filling material being thermally conductive and comprising a thermosetting epoxy resin. (see Par.[0018]-[0020] wherein the first underfill material 110 and/or the
second underfill material 120 may be or comprise various types of underfill polymers, such as may
comprise epoxy (i.e.; epoxy is a type of thermosetting polymer), silicone, phosphine oxide, polyethylene/polypropylene copolymers, and/or urethane
polymers, including resin transfer molding (low pressure) and injection transfer molding (high pressure),
among other examples).
With respect to claim 18, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
second plurality of electrical connections comprises a ball grid array.
With respect to claim 19, Wang discloses, in Figs.2-8, a semiconductor device comprising: a
substrate (10) comprising a first top surface and a first bottom surface, the first top surface comprising a
first plurality of electrical contacts (710), the first bottom surface comprising a second plurality of electrical
contacts/(contacts on lower surface of chip) (see Par.[0027] wherein FIG. 7 is a sectional view of an
implementation of the apparatus 100 shown in FIG. 3 in which conductive members 710 are formed in
and/or on the surface of the first side 12 of the first substrate 10); a ring structure (60) positioned on a first
location of the first top surface; a first plurality of electrical connections (40) directly coupled to the first
plurality of electrical contacts, the first plurality of electrical connections being positioned within the ring
structure; a circuit (30) comprising a second top surface and a second bottom surface, the second bottom
surface comprising a second plurality of electrical contacts, the second plurality of electrical contacts
being directly coupled to the first plurality of electrical connections, the circuit further comprising a first
side surface and a second side surface; and a filling material (120) comprising a first portion and a
second portion, the first portion being directly coupled to the first plurality of electrical connections and the
second bottom surface, the second portion being in direct contact with the first side surface and the ring
structure, a height difference between the second portion the second top surface being less 100µm, the filling material being thermally conductive and comprising a thermosetting epoxy resin. (see
Par.[0026] wherein FIG. 4 is a plan view of the apparatus 100 shown in FIGS. 1-3, illustrating that the
dam structure 60 may comprise a continuous barrier extending around the IC memory chip 30 and the
plurality of first conductive members 40 (which are obstructed from view in FIG. 4); see Par.[0021]-[0024]
wherein the dam structure 60 may comprise one or more layers of conductive and/or dielectric materials,
such as copper, aluminum, doped polysilicon, titanium, titanium nitride, tantalum nitride, titanium, silicon
nitride, silicon oxide, combinations and/or alloys thereof, and/or other materials, and may be formed utilizing chemical-vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal organic CVD
(MOCVD), sputtering, epitaxial growth, and/or other processes; see Par.[0052] wherein the dam structure
may comprise a member having a width and a height, wherein the member extends around a substantial
portion of the plurality of first conductive members; in some embodiments, the width may be about 20
microns and the height may be about 12 microns (i.e.; < 100 microns); see Par.[0022] wherein he dam
structure 60 may be or comprise one or more members each having a width W and a thickness T; the
width W may range between about five microns and about forty microns, such as in implementations in
which the width W is about twenty microns, although other dimensions are also within the scope of the
present disclosure; the thickness T may range between about four microns and about twenty microns,
such as in implementations in which the thickness T is about twelve microns, although other dimensions
are also within the scope of the present disclosure; see Par.[0018]-[0020] wherein the first underfill
material 110 and/or the second underfill material 120 may be or comprise various types of underfill
polymers, such as may comprise epoxy (i.e.; epoxy is a type of thermosetting polymer), silicone, phosphine oxide, polyethylene/polypropylene copolymers, and/or urethane polymers, including resin transfer molding (low pressure) and injection transfer molding (high pressure), among other examples).
With respect to claim 20, Wang discloses, in Figs.2-8, the semiconductor device, wherein the
filling material comprises a third portion positioned W the circuit and the ring structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
With respect to claim 7, Wang discloses all the claimed limitations of claim 5. Wang further discloses in Figs.2-8, the semiconductor device, wherein a fifth side surface is at least a distance below the second top surface.
Even though Wang does not disclose a fifth side surface is at least 20 µm below the second top surface, the said range is predictable by simple engineering optimization motivated by a design choice, such as, overall cost-effective dimensions of device. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
With respect to claim 8, Wang discloses all the claimed limitations of claim 7. Wang further discloses in Figs.2-8, the semiconductor device, wherein a fifth side surface is at least a distance below the second top surface.
Even though Wang does not disclose the fifth side surface being at least one-eighth of the first height below the second top surface, the said range is predictable by simple engineering optimization motivated by a design choice, such as, overall cost-effective dimensions of device. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
Response to Arguments
Applicant’s arguments with respect to claims 1, 17, 19 have been considered but are moot because the current rejection does not rely on the prior rejection of record for all teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818