DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 12/29/2025 is acknowledged. Claims 11-20 are hereby withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6, 8 and 10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Javier (US 20110248392), hereinafter Javier.
Regarding claim 1, Javier (refer to Figures 1-7; also see Note 1 below) teaches an electronic device (100 or 300, see para 24 and 33) comprising:
a leadframe (110, described as "leadframe 110" in para 24; best seen in Figure 1; a leadframe only view is shown in Figure 5 – see para 38) having a plurality of contact pads (pads of leadframe to which contact and bond to “bonding wires 223” or “metal bumps 323”, such as ACP in markup of Figure 2 below), at least two adjacent contact pads (ACP, see markup of Figure 2 below) of the plurality of contact pads being disconnected from each other via a slot (SL, see markup of Figure 2 below, noting that SL ensures adjacent leads are not shorted);
a die (120 of Figure 2 or 320 of Figure 3, described as "semiconductor chip" in para 25 and 33) having a plurality of input/output pins (222 of Figure 2 or it’s equivalent in Figure 3 – not labelled, described as "input/output pads 222 of chip 120" in para 32; best seen in Figure 2), the plurality of input/output pins connected to (by “bonding wires 223” or “metal bumps 323”, as explained above) respective contact pads of the plurality of contact pads on the leadframe;
a plurality of interconnects (223 of Figure 2 or 323 of Figure 3, described as "bonding wires 223" in para 32 and "bumps 323" in para 33) connecting the plurality of input/output pins (222 of Figure 2 or it’s equivalent in Figure 3) to the respective contact pads; and
a mold compound (140, described as "polymeric material of package 140" in para 30; see Figure 2, not labelled in Figure 3) encapsulating the die (120 of Figure 2 or 320 of Figure 3) and the plurality of interconnects (223 of Figure 2 or 323 of Figure 3).
Note 1: Referring to para 16-23 of Javier, Figures 1-7 show substantially the same embodiment except that Figures 3 and 7, explained in para 33-34 are for devices 300 where “semiconductor chip 320 is flip-attached to the leadframe by metal bumps 323” while in Figure 2, “bonding wires 223, enabling the connection of input/output pads 222 of chip 120” (see para 32) for device 100. In other words, only the interconnection technique is different; i.e. wire-bonding in Figure 2 vs flip-chip bumps in Figure 3, and as such, both these interconnection techniques are taught in the context of the lead frame.
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Regarding claim 2, Javier (refer to Figures 1-7) teaches the electronic device of claim 1, wherein the leadframe further includes a plurality of leads (111, described as "leads 111" having "terminals 112" that are "exposed from" the material of 140 - see para 26; also see equivalent terminals 312 in FIgure 3) that are connected to the plurality of contact pads (pads of leadframe to which contact and bond to “bonding wires 223” or “metal bumps 323”), the plurality of leads extending away from at least one side of the mold compound (so that they are "exposed from" the material of 140 - see para 26).
Regarding claim 6, Javier (refer to Figures 1-7) teaches the electronic device of claim 1, the plurality of input/output pins of the die are connected to the plurality of contact pads of the leadframe via electrically conductive pillars and interconnects (para 10 describes option of “copper pillars” when “chip may be flipped and bonded”).
Regarding claim 8, Javier (refer to Figures 1-7) teaches the electronic device of claim 1, wherein the leadframe may be plated with a nickel palladium plating (para 31). Whereas claim 8 is a product claim, the claim recites a method of steps therein, i.e. “electroplated with” (because electroplating is a specific process of coating). Therefore, the claim amounts to a product by process claim. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
Regarding claim 10, Javier (refer to Figures 1-7) teaches the electronic device of claim 1, wherein the die is a flip-chip die (para 33 describes "semiconductor chip 320 is flip-attached to the leadframe").
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Javier in view of Lin (US 20170301617), hereinafter Lin.
Regarding claim 3, Javier (refer to Figures 1-7) teaches the electronic device of claim 2, wherein the leads of the leadframe have solderable metallurgical surface configuration (para 26) that may be achieved by coating a layer of a solderable material such as gold (para 31) but does not teach that the layer of solderable material is “a solder plating”. Lin (US 20170301617) that it is known to selectively selectively plated with not only gold, but any other solderable metal including lead-tin solder (para 88). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Javier so that the layer of solderable material is “a solder plating”. The ordinary artisan would have been motivated to modify Javier for at least the purpose of facilitating means of electrically connecting exposed parts of leads to other components of the circuit by a common method such as soldering (para 27 of Javier).
Whereas claim 3 is a product claim, the claim recites a method of steps therein, i.e. “electroplated with” (because electroplating is a specific process of coating). Therefore, the claim amounts to a product by process claim. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Javier.
Regarding claim 4-5, Javier (refer to Figures 1-7) teaches the electronic device of claim 1, but does not specifically state that a number of the plurality of input/output pins of the die is “the same as” (as recited in claim 4) or “less than” (as recited in claim 5) a number of the plurality of contact pads of the leadframe. However, Figure 2 of Javier shows a configuration wherein each contact pad (such as ACP in markup of Figure 2 above) of the leadframe is bonded by a single bonding wires (223) to each of the corresponding input/output pin (222), and such an arrangement (where no leads are shared) requires at least as many contact pads of the leadframe as the number of input/output pins of the die; i.e. input/output pins of the die is “the same as” (as recited in claim 4) or “less than” (as recited in claim 5) a number of the plurality of contact pads of the leadframe . It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Javier so that input/output pins of the die is “the same as” (as recited in claim 4) or “less than” (as recited in claim 5) a number of the plurality of contact pads of the leadframe. The ordinary artisan would have been motivated to modify Javier for at least the purpose of using a leadframe with a die where each input/output pin carries a unique signal to ensure each signal is able to connect to a unique contact pad, while extra contact pads may be made available for larger currents like power.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Javier in view of Noquil (US 20210090980), hereinafter Noquil.
Regarding claim 7, Javier (refer to Figures 1-7) teaches the electronic device of claim 1, but does not disclose that the die includes “a passivation layer disposed on an active surface of the die”. Noquil (US 20210090980) teaches it is known in the art to position a passivation layer to protect the active area of a semiconductor device (para 50). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Javier so that the die includes “a passivation layer disposed on an active surface of the die”. The ordinary artisan would have been motivated to modify Javier for at least the purpose of ensuring that the active area of the semiconductor device is not directly exposed to air or moisture from surrounding, so that the lifetime of the semiconductor device is extended (para 50 of Noquil).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Javier in view of Sham (US 20090293604), hereinafter Sham.
Regarding claim 9, Javier (refer to Figures 1-7) teaches the electronic device of claim 1, but does not teach that the electronic device is “one of a single in-line integrated circuit package and a dual in-line integrated circuit package”. Sham teaches electronic device comprising leadframe (para 22) and that it is known in the art that they may utilize a wide range of package types including single in-line or dual in-line integrated circuit packages (para 63). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Javier for a well known package type, such as “one of a single in-line integrated circuit package and a dual in-line integrated circuit package”. The ordinary artisan would have been motivated to modify Javier for at least the purpose of using known package type such as dual in-line packages that are used by large number of end users and provide a larger number of input/output terminals compared to single in-line packages and require less complex soldering compared to ball grid array packages.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Flores (US 20140071650).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJAY ARORA whose telephone number is (571)272-8347. The examiner can normally be reached 9 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 5712721736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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