Prosecution Insights
Last updated: July 17, 2026
Application No. 18/297,971

DUAL-SIDED MOLDED PACKAGE WITH EXPOSED BACKSIDE DIE FOR THERMAL DISSIPATION

Final Rejection §103
Filed
Apr 10, 2023
Priority
Apr 11, 2022 — provisional 63/362,814
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Skyworks Solutions Inc.
OA Round
2 (Final)
50%
Grant Probability
Moderate
3-4
OA Rounds
5m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allowance Rate
7 granted / 14 resolved
-18.0% vs TC avg
Strong +47% interview lift
Without
With
+46.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
38 currently pending
Career history
72
Total Applications
across all art units

Statute-Specific Performance

§103
85.2%
+45.2% vs TC avg
§102
11.4%
-28.6% vs TC avg
§112
3.4%
-36.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings filed April 9 2026 overcome the previous drawing objections. The drawing objections have been withdrawn. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 4-10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over by Liu et al. (“Liu” US Patent No. 12,009,312) and Nomura et al. (“Nomura” US 2020/0137893) as evidenced by Kim et al. (“Kim” US 2016/0300774). Regarding claim 1, Liu discloses a dual-sided molded package module (Figure 7) comprising: a substrate (700) having a top side and a bottom side opposite the top side (see Figure 7); a die (“device component”, col. 12 lines 20-21, adjacent to die 712, see Figure 7) attached to the bottom side of the substrate (700, see Figure 7), the die having a first height (the device component adjacent to die 712 has a certain thickness in the vertical direction, or a height in a vertical direction, see Figure 7); a plurality of posts (714-2, upper portion) attached to the bottom side of the substrate (700) and being laterally spaced from the die (device component adjacent to die 712, see Figure 7); a bottom mold (710) surrounding and extending between the plurality of posts (714-2) and the die (device component adjacent to die 712, see Figure 7), the bottom mold (710) having a second height (thickness in a vertical direction, see Figure 7) that is greater than the first height (thickness of the device component adjacent to die 712, the total thickness of the bottom mold is greater than the thickness of the die/device component, see Figure 7); a plurality of electrically and thermally conductive interconnect members (714-2, lower portion) attached to the plurality of posts (714-2, upper portion) and extending through the bottom mold (710, see Figure 7); and a thermally conductive layer (shielding member 732, analogous to shielding members 134/132 of Figure 1, has heat dissipation properties, see col. 5, line 62 – col. 6, line 5 and col. 12 lines 22-25) attached to a bottom facing surface of the die (device component adjacent to die 712, the thermally conductive member 732 is attached to the bottom surface of the die through the bottom mold 710, see Figure 7), the thermally conductive layer (732) extending through the bottom mold (portions of the layer 732 extend through the bottom mold to contact interconnects) and configured to couple to a motherboard (750, see Figure 7), the thermally conductive layer (732) configured to dissipate heat from the die (component adjacent to die 712 is thermally connected to the thermally conductive layer through the bottom mold 710, thus would dissipate heat) to the motherboard (750, pads 752-1 have heat exchanging properties, see col. 12, lines 35-37). Liu does not disclose that the bottom mold has a recess above at least a portion of the die or that the thermally conductive layer is in the recess of the bottom mold. Nomura discloses in Figure 1, however, a bottom mold (5, considered a bottom mold when Figure 1 is inverted) having a recess (10) above at least a portion of the die (4, see Figure 1), the thermally conductive layer (shield 6, formed of copper, para. [0049], thus is thermally conductive) in the recess (10) of the bottom mold (5, see Figure 1). It would have bene obvious to a person having ordinary skill in the art to incorporate the teachings of Nomura into the teachings of Liu to include the recess in the bottom mold, where the thermally conductive layer extends into the mold over at least a portion of the die for the purpose of increasing the amount of heat transfer between the die and the thermally conductive layer due to direct physical contact therebetween, as evidenced by Kim (see Kim’s heat spread 150 and semiconductor chip 130, para. [0106]). Regarding claim 2, Nomura discloses wherein the recess (10) and the thermally conductive layer (6) extend entirely across the bottom facing surface (inverted Figure 1) of the die (4, the lateral dimension of the recess 10 and the thermally conductive layer extend farther than the lateral dimension of the top surface, bottom facing surface when Figure 1 is inverted, of the die 4). Regarding claim 4, Liu discloses wherein the thermally conductive layer (732) is separated from the electrically and thermally conductive interconnect members (714-2, lower portion) by the bottom mold (710, see Figure 7). Regarding claim 5, Liu discloses wherein the electrically and thermally conductive interconnect members (714-2, lower portion) have a greater lateral dimension than the posts (714-2, upper portion, see Figure 7, the interconnects 714-2 that comprise the interconnect members and posts have a tapered shape, where the top portion is narrower than the bottom portion). Regarding claim 6, Liu further discloses one or more electronic components (see plurality of components on the upper surface of the substrate in Figure 7) connected to the top side of the substrate (700) and a top mold disposed over the electronic components (720, see Figure 7). Regarding claim 7, Liu further discloses a shield (734) disposed over the top mold (720) and a side of the substrate (700, see Figure 7). Regarding claim 8, Liu discloses a wireless device (Figure 7) comprising: a motherboard (750); and a dual-sided molded package module mounted on the motherboard (750, see Figure 7), the dual-sided molded package module including a substrate (700) having a top side and a bottom side opposite the top side (see Figure 7), a die (“device component”, col. 12 lines 20-21, adjacent to die 712) attached to the bottom side of the substrate (700, see Figure 7), the die having a first height (the device component adjacent to die 712 has a certain thickness in the vertical direction, or a height in a vertical direction, see Figure 7), a plurality of posts (714-2, upper portion) attached to the bottom side of the substrate (700) and being laterally spaced from the die (device component adjacent to die 712, see Figure 7), a bottom mold (710) surrounding and extending between the plurality of posts (714-2) and the die (device component adjacent to die 712, see Figure 7), the bottom mold (710) having a second height (thickness in a vertical direction, see Figure 7) that is greater than the first height of the die (thickness of the device component adjacent to die 712, the total thickness of the bottom mold is greater than the thickness of the die/device component, see Figure 7), a plurality of electrically and thermally conductive interconnect members (714-2, lower portion) attached to the plurality of posts (714-2, upper portion) and extending through the bottom mold (710, see Figure 7), and a thermally conductive layer (shielding member 732, analogous to shielding members 134/132 of Figure 1, has heat dissipation properties, see col. 5, line 62 – col. 6, line 5 and col. 12 lines 22-25) attached to a bottom facing surface of the die (device component adjacent to die 712 is attached to the thermally conductive layer 732 through the bottom mold 710), the thermally conductive layer (732) extending through the bottom mold (portions of the layer 732 extend through the bottom mold to contact interconnects) and coupled to the motherboard (750), the thermally conductive layer (732) is configured to dissipate heat from the die (device component adjacent to die 712 is thermally connected to the thermally conductive layer through the bottom mold 710, thus would dissipate heat) to the motherboard (750, pads 752-1 have heat exchanging properties, see col. 12, lines 35-37). Liu does not disclose that the bottom mold has a recess above at least a portion of the die or that the thermally conductive layer is in the recess of the bottom mold. Nomura discloses in Figure 1, however, a bottom mold (5, considered a bottom mold when Figure 1 is inverted) having a recess (10) above at least a portion of the die (4, see Figure 1), the thermally conductive layer (shield 6, formed of copper, para. [0049], thus is thermally conductive) in the recess (10) of the bottom mold (5, see Figure 1). It would have bene obvious to a person having ordinary skill in the art to incorporate the teachings of Nomura into the teachings of Liu to include the recess in the bottom mold, where the thermally conductive layer extends into the mold over at least a portion of the die for the purpose of increasing the amount of heat transfer between the die and the thermally conductive layer due to direct physical contact therebetween, as evidenced by Kim (see Kim’s heat spread 150 and semiconductor chip 130, para. [0106]). Regarding claim 9, Liu discloses wherein the thermally conductive layer (732) is coupled to the motherboard (750) via a solderable material (interconnects between motherboard 750 and the thermally conductive layer 732) attached to the thermally conductive layer (732, see Figure 7). Regarding claim 10, Nomura discloses wherein the recess (10) and the thermally conductive layer (6) extend entirely across the bottom facing surface (inverted Figure 1) of the die (4, the lateral dimension of the recess 10 and the thermally conductive layer extend farther than the lateral dimension of the top surface, bottom facing surface when Figure 1 is inverted, of the die 4). Regarding claim 12, Liu discloses wherein the thermally conductive layer (732) is separated from the electrically and thermally conductive interconnect members (714-2, lower portion) by the bottom mold (710, see Figure 7). Regarding claim 13, Liu discloses wherein the electrically and thermally conductive interconnect members (714-2, lower portion) have a greater lateral dimension than the posts (714-2, upper portion, see Figure 7, the interconnects 714-2 that comprise the interconnect members and posts have a tapered shape, where the top portion is narrower than the bottom portion). Regarding claim 14, Liu further discloses one or more electronic components (see plurality of components on the upper surface of the substrate in Figure 7) connected to the top side of the substrate (700) and a top mold disposed over the electronic components (720, see Figure 7). Regarding claim 15, Liu further discloses a shield (734) disposed over the top mold (720) and a side of the substrate (700, see Figure 7). Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (first embodiment of Figure 7), Nomura, and Kim as applied to claims 1 and 8 above, and further in view of a second embodiment of Liu (Figure 12G). Regarding claim 3, Liu discloses that the thermally conductive layer may be formed of copper (see col. 7, lines 1-20). Liu discloses in another embodiment (Figure 12G) that the electrically and thermally conductive interconnect members (714-2 in Figure 7) can be made of copper as well (see col. 17, lines 1-2). Thus, the two embodiments of Liu disclose that the electrically and thermally conductive interconnect members (714-2, 1214 in Figure 12G) are made of a same material as the thermally conductive layer (732). It would have been obvious to one having ordinary skill in the art to use the same material, copper as taught by Liu, for the thermally and electrically conductive interconnect members and the thermally conductive layer because copper has excellent thermal dissipation and electrical conductivity properties (see col. 7, lines 1-20). Further, using the same material for different parts of a device can simplify the fabrication process. Regarding claim 11, Liu discloses that the thermally conductive layer may be formed of copper (see col. 7, lines 1-20). Liu discloses in another embodiment (Figure 12G) that the electrically and thermally conductive interconnect members (714-2 in Figure 7) can be made of copper as well (see col. 17, lines 1-2). Thus, the two embodiments of Liu disclose that the electrically and thermally conductive interconnect members (714-2, 1214 in Figure 12G) are made of a same material as the thermally conductive layer (732). It would have been obvious to one having ordinary skill in the art to use the same material, copper as taught by Liu, for the thermally and electrically conductive interconnect members and the thermally conductive layer because copper has excellent thermal dissipation and electrical conductivity properties (see col. 7, lines 1-20). Further, using the same material for different parts of a device can simplify the fabrication process. Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, Nomura, and Kim as applied to claims 1 and 8 above, and further in view of Juskey et al. (“Juskey” US 2013/0234344). Regarding claim 21, Liu, Nomura, and Kim do not disclose specifically that the dual-sided molded package module is a power amplifier module. However, Liu discloses that the package can comprise active or passive components, which would include a power amplifier (see col. 7, lines 28-40). Juskey discloses a power amplifier module package (see para. [0061]-[0062]). It would have been obvious to one having ordinary skill in the art to incorporate the power amplifier package module components of Juskey into the active/passive components of the combination of Liu, Nomura, and Kim to form a dual-sided amplifier module because deciding the functionality of a device and the components therein is within the skillset of one having ordinary skill in the art, and active/passive components are both included in a power amplification package. Regarding claim 22, Liu, Nomura, and Kim not disclose specifically package module is a power amplifier. However, Liu discloses that the package can comprise active or passive components, which would include a power amplifier (see col. 7, lines 28-40). Juskey discloses a package module comprising a power amplifier (see para. [0061]-[0062]). It would have been obvious to one having ordinary skill in the art to incorporate the power amplifier package module components of Juskey into the active/passive components of the combination of Liu, Nomura, and Kim because deciding the functionality of a device and the components therein is within the skillset of one having ordinary skill in the art, and active/passive components are both included in a power amplification package. Regarding claim 23, Liu, Nomura, and Kim do not disclose specifically that the device includes a transceiver. However, Liu discloses that the package can comprise active or passive components, which would include a transceiver (see col. 7, lines 28-40). Juskey discloses a device comprising a transceiver (see para. [0061]-[0062]). It would have been obvious to one having ordinary skill in the art to incorporate a transceiver into the device of the combination of Liu, Nomura, and Kim for the purpose of receiving and sending signals (Juskey, para. [0062]). Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (“Liu” US Patent No. 12,009,312) and Nomura et al. (“Nomura” US 2020/0137893) as evidenced by Kim et al. (“Kim” US 2016/0300774), and Elsherbini et al. (“Elsherbini US 2022/0406751). Regarding claim 24, Liu discloses: a circuit board (750); a dual-sided molded package module mounted on the circuit board (750, see Figure 7), the dual-sided molded package module including a substrate (700) having a top side and a bottom side opposite the top side (see Figure 7), a die (device component, col. 12, lines 20-21, adjacent to die 712) attached to the bottom side of the substrate (700, see Figure 7), the die having a first height (the device component adjacent to die 712 has a certain thickness in the vertical direction, or a height in a vertical direction, see Figure 7), a plurality of posts (714-2, upper portion) attached to the bottom side of the substrate (700) and being laterally spaced from the die (device component adjacent to die 712, see Figure 7), a bottom mold (710) surrounding and extending between the plurality of posts (714-2) and the die (device component adjacent to die 712, see Figure 7), the bottom mold (710) having a second height (thickness in a vertical direction, see Figure 7) that is greater than the first height of the die (thickness of the device component adjacent to die 712, the total thickness of the bottom mold is greater than the thickness of the die/device component, see Figure 7), a plurality of electrically and thermally conductive interconnect members (714-2, lower portion) attached to the plurality of posts (714-2, upper portion) and extending through the bottom mold (710, see Figure 7), and a thermally conductive layer (shielding member 732, analogous to shielding members 134/132 of Figure 1, has heat dissipation properties, see col. 5, line 62 – col. 6, line 5 and col. 12 lines 22-25) attached a bottom facing surface of the die (device component adjacent to die 712), the thermally conductive layer (732) extending through the bottom mold (portions of the layer 732 extend through the bottom mold to contact interconnects) and coupled to the circuit board (750), the thermally conductive layer (732) is configured to dissipate heat from the die (device component adjacent to die 712, connected through bottom mold 710, thus would dissipate heat) to the circuit board (750, pads 752-1 have heat exchanging properties, see col. 12, lines 35-37). Liu does not disclose that the bottom mold has a recess above at least a portion of the die or that the thermally conductive layer is in the recess of the bottom mold. Nomura discloses in Figure 1, however, a bottom mold (5, considered a bottom mold when Figure 1 is inverted) having a recess (10) above at least a portion of the die (4, see Figure 1), the thermally conductive layer (shield 6, formed of copper, para. [0049], thus is thermally conductive) in the recess (10) of the bottom mold (5, see Figure 1). It would have bene obvious to a person having ordinary skill in the art to incorporate the teachings of Nomura into the teachings of Liu to include the recess in the bottom mold, where the thermally conductive layer extends into the mold over at least a portion of the die for the purpose of increasing the amount of heat transfer between the die and the thermally conductive layer due to direct physical contact therebetween, as evidenced by Kim (see Kim’s heat spread 150 and semiconductor chip 130, para. [0106]). Liu, Nomura, and Kim do not disclose specifically that a wireless phone board comprises the following elements of the claim, or a transceiver module mounted on the circuit board. Elsherbini discloses a wireless phone board (2400, para. [0115] discloses that 2400 may be a cell phone or smart phone, and para. [0101] discloses that phone board 2400 may comprise the IC packages and devices of the preceding disclosed embodiments) comprising a transceiver module (para. [0026], components associated with IC structures of the embodiments disclosed may be transceivers) mounted on a circuit board (2400 may be mounted/attached to one or more motherboards, see para. [0102]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of the phone board and transceiver of Elsherbini into the combination of Liu, Nomura, and Kim because it is within the skillset of one having ordinary skill in the art to assemble a device with interconnected IC components is accordance with an intended functionality or application of the device (see Elsherbini, para. [0020]). Further, Liu discloses that the devices disclosed may be active or passive devices, which implies that the functionality of the device as a whole can be determined according to the parameters set forth by the device for which one having ordinary skill in the art is using the package structures of Liu. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Liu, Nomura, Kim, and Elsherbini as applied to claim 24 above, and further in view of Juskey et al. (“Juskey” US 2013/0234344). Regarding claim 25, Liu, Nomura, Kim, and Elsherbini do not disclose specifically that the dual-sided molded package module includes a power amplifier. However, Liu discloses that the package can comprise active or passive components, which would include a power amplifier (see col. 7, lines 28-40). Juskey discloses a power amplifier module package (see para. [0061]-[0062]). It would have been obvious to one having ordinary skill in the art to incorporate the power amplifier package module components of Juskey into the active/passive components of the combination of Liu, Nomura, Kim, and Elsherbini to form a dual-sided amplifier module because deciding the functionality of a device and the components therein is within the skillset of one having ordinary skill in the art, and active/passive components are both included in a power amplification package. Response to Arguments Applicant’s amendments filed April 9 2026 with respect to the objections to claims 1 and 23 have been fully considered and overcome the objections. The objections to claims 1 and 23 have been withdrawn. Applicant’s arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any interpretation of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 10, 2023
Application Filed
Nov 14, 2025
Non-Final Rejection mailed — §103
Apr 09, 2026
Response Filed
May 29, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 3 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
50%
Grant Probability
97%
With Interview (+46.7%)
3y 8m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allowance rate.

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