Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Currently, the title has been changed to:
“GATE-ALL-AROUND TRANSISTOR STRUCTURES WITH DIFFERENT CHANNEL LAYERS AND METHOD FOR FORMING THE SAME”
Election/Restrictions
Applicant’s election without traverse of invention II, drawn to claims 15-20 and newly added claims 21-34, in the reply filed on 11/17/2025, is acknowledged. Claims 1-14 have been canceled.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (Pub. No. US 2019/0067122 A1, herein Cheng).
Regarding claim 15, Cheng discloses a method for forming an integrated circuit, comprising: forming first and second stacks of alternating first semiconductor layers 103/107/111/115 and second semiconductor layers 105/109/113/117 over first and second regions 106-108 of a substrate 101 (Cheng: Figs. 1A-1B and paragraphs [0020]-[0021]), respectively, wherein a thickness of each of the first semiconductor layers is controlled such that quantum confinement occurs in each of the first semiconductor layers (Cheng: paragraphs [0025]-[0034]; Quantum confinement is the phenomenon in which electrons and holes are spatially restricted to very small dimensions, typically nanometer scale, causing their energy levels to become discrete rather than continuous and significantly changing the material’s electrical and optical behavior. A nanowire shows quantum confinement because it is so thin that electrons cannot move freely and are forced into specific energy states.); forming first source and drain structures 601 on opposite sides of the first semiconductor layers of the first stack; forming second source and drain structures 603 on opposite sides of the second semiconductor layers of the second stack (Cheng: Figs. 2-8 and paragraphs [0073]-[0076]); removing first portions of the second semiconductor layers of the first stack, while leaving first portions of the first semiconductor layers of the first stack suspended over the substrate; removing second portions of the first semiconductor layers of the second stack, leaving second portions of the second semiconductor layers the second stack suspended over the substrate (Cheng: Figs. 9A-10B and paragraphs [0069]-[0089]); forming a first gate structure 1101-1103 wrapping around each of the first portions of the first semiconductor layers of the first stack and a second gate structure 1101-1103 wrapping around each of the second portions of the second semiconductor layers of the second stack (Cheng: Figs. 11-12 and paragraphs [0098]-[0100]); and forming an interconnect structure 1105-1107 electrically coupling the first source structure and the second drain structure (Cheng: paragraphs [0106]-[0108]).
Regarding claim 19, Cheng discloses the method of claim 15, further comprising: forming a first dummy gate structure 119-121 and a second dummy gate structure 119-121 over the first region and the second region of the substrate, respectively (Cheng: Figs. 1A-1B and paragraphs [0041]-[0043], [0055]); removing the first dummy gate structure to form a first gate trench, wherein removing the first portions of the second semiconductor layers is performed in the first gate trench; and removing the second dummy gate structure to form a second gate trench, wherein removing the second portions of the first semiconductor layers is performed in the second gate trench (Cheng: Figs. 2-10B and paragraphs [0078]-[0082]).
Regarding claim 20, Cheng discloses the method of claim 15, wherein the interconnect structure further comprises: a power supply terminal electrically coupled to the first drain structure; an input terminal electrically coupled to the second gate structure; and an output terminal electrically coupled to the first drain structure (Cheng: Fig. 12 and paragraphs [0021]-[0022], [0064]-[0066]; I/O 104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 16-17, 21-26, 28-29 and 30-34 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Cheng et al. (Pub. No. US 2017/0062428 A1, herein Cheng-28).
Regarding claims 16 and 30, Cheng does not specifically state wherein a thickness of each of the second semiconductor layers is greater than the thickness of each of the first semiconductor layers, such that no quantum confinement occurs in the second semiconductor layers.
However, in the same field of endeavor, Cheng-28 in paragraphs [0004], [0033]-[0034] teaches a thickness of each of the second semiconductor layers is greater than the thickness of each of the first semiconductor layers, such that no quantum confinement occurs in the second semiconductor layers to allow different devices be placed on the same substrate; for example to enable tensily strained silicon nanowires within an nFET device region of a substrate, and compressively strained silicon germanium alloy (SiGe) nanowires in a pFET device region of the same substrate (Cheng-28: paragraph [0005]).
Therefore, given the teachings of Cheng-28, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Cheng in view of Cheng-28 by employing the thickness of each of the second semiconductor layers being greater than the thickness of each of the first semiconductor layers, such that no quantum confinement occurs in the second semiconductor layers.
Regarding claims 17 and 31, Compressively strained SiGe and tensile strained SiGe do not have the same bandgap, even if the Ge composition is the same. Compressively strained SiGe has smaller bandgap than unstrained SiGe. A thin SiGe layer is fully strained, and a thicker SiGe layer is partially or fully relaxed. Ultra-thin SiGe layer is strained and has confinement. Therefore, Cheng in view of Cheng-28 teaches the method of claim 16, wherein a bandgap of a material of the first semiconductor layers is larger than a bandgap of a material of the second semiconductor layers.
Regarding claims 21 and 29, the applicant is referred to the rejections applied to claims 1, 16 and 17.
Regarding claim 22, Cheng in view of Cheng-28 teaches the method of claim 21, wherein the thickness of each of the first semiconductor layers is in a range from about 0.5 nm to about 5 nm, and the thickness of each of the second semiconductor layers is in a range from about 2 nm to about 50 nm (Cheng: paragraphs [0025], [0028]-[0034] and Cheng-28: paragraphs [0033]-[0034]).
Regarding claim 23, Cheng in view of Cheng-28 teaches the method of claim 21, wherein one of the first semiconductor layers is a quantum well (Cheng: paragraphs [0025], [0028]-[0034] and Cheng-28: paragraphs [0033]-[0034]).
Regarding claim 24, Cheng in view of Cheng-28 teaches the method of claim 21, further comprising forming an interconnection structure electrically coupling the first source structure to the second drain structure (Cheng: paragraphs [0106]-[0108]).
Regarding claims 25-26 and 32-34, Cheng in view of Cheng-28 teaches the method of claim 24, wherein the interconnection structure comprises a power supply terminal electrically coupled to the first drain structure, and wherein the second source structure is grounded, wherein the interconnection structure comprises: an input terminal electrically coupled to the second gate structure; and an output terminal electrically coupled to the first drain structure (Cheng: Fig. 12 and paragraphs [0021]-[0022], [0064]-[0066]; I/O 104).
Regarding claim 28, Cheng in view of Cheng-28 teaches the method of claim 21, wherein a material of the first semiconductor layers is different from a material of the second semiconductor layers (Cheng: paragraphs [0024], [0027]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Agrawal et al. (Pub. No. US 2023/0147499 A1, herein Agrawal).
Regarding claim 18, Cheng does not specifically state wherein the first semiconductor layers and the second semiconductor layers are made of silicon germanium but with different germanium concentrations.
However, in the same field of endeavor, Agrawal in paragraphs [0019] and [0038] teaches wherein the first semiconductor layers and the second semiconductor layers are made of silicon germanium but with different germanium concentrations to optimize performance, power and functionality, since different applications demand different tradeoffs between mobility, leakage, confinement, power handling and speed.
Therefore, given the teachings of Agrawal, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Cheng in view of Agrawal by employing the different germanium concentration.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Cheng-28, as applied above, and further in view of Radosavljevic et al. (Pub. No. US 20/0 A1, Radosavljevic).
Regarding claim 27, the previous combination does not specifically state the first semiconductor layers are offset from the second semiconductor layers along a vertical direction.
However, in the same field of endeavor, Radosavljevic in paragraphs [0037] and [0040] teaches the first semiconductor layers being offset from the second semiconductor layers along a vertical direction to provide well matched n-type and p-type devices (Radosavljevic: paragraph [0004]).
Therefore, given the teachings of Radosavljevic, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Radosavljevic by employing the offset configuration.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
January 8, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813