DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I (claims 1-8 and 17-20) in the reply filed on 06/16/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US Patent: 10332999 B1), herein after Cheng, in view of Lim et al. (US PGPub: 2022/0102266 A1), herein after Lim.
Regarding claim 1, Cheng teaches a semiconductor structure comprising:
an array of transistors (array of transistors having active and dummy transistors) on a semiconductor substrate (202, FIG 11), the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and
wherein the connection connects a first contact at a frontside of the array of transistors to a second contact at a backside of the array of transistors (FIG. 10A or aa where frontside connect to backside of array transistor).
Cheng does not explicitly a metal connection between the first transistor and the second transistor.
However, Lim teaches metal connection between the first transistor and the second transistor wherein connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors (FIG. 1A, where 108A, 108B and metallization structure interconnect transistor different FETs.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Cheng’s transistor with teachings by Lim so that device power routing can be done efficiently without disturbing adjacent routing areas.
Regarding claim 2, Cheng teaches the semiconductor structure of claim 1, wherein a source/drain region of the first transistor and a source/drain region of the second transistor are filled with the metal connection (170, FIG 10A, The gate layers 170 can include, for example, a work-function metal (WFM) layer, including but not necessarily limited to, for a PFET, titanium nitride (TiN), tantalum nitride (TaN) or ruthenium (Ru), and for an NFET, TiN, titanium aluminum nitride (TiAlN), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum carbon nitride (TaAlCN) or lanthanum (La) doped TiN, TaN. The gate layers 170 may further include, but are not necessarily limited to, metals, such as, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, and/or copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof deposited on the WFM layer), rendering the first transistor being a first dummy transistor and the second transistor being a second dummy transistor (as in FIG. 11).
Regarding claim 3, Cheng teaches (in view of Lim) the semiconductor structure of claim 2, wherein the first dummy transistor includes a first dummy gate that surrounds a first set of nanosheets, the first set of nanosheets has a first section adjacent to the metal connection and a second section adjacent to a source/drain region of an active transistor, wherein the first section and the second section of the first set of nanosheets comprise different material. Nanosheets are taught in Lim which are 18P in FIG. 1B. Nano sheets are adjacent to source/drain region of Active transistor FET 116. 128P can be separated into multiple sections. One section can be closer to Source/drain region and other section can be closer to metal connection. Cheng does not teach the nanosheets, so nanosheet are combined from Lim reference.
Regarding claim 4, Cheng teaches (in view of Lim) the semiconductor structure of claim 3, wherein the first section of the first set of sheets comprises a dielectric material (205’ in FIG. 11) and the second section of the first set of nanosheets comprises a silicon material , and the first section of the first set of sheets electrically isolates the metal connection from the second section of the first set of nanosheets. Nano sheets are adjacent to source/drain region of Active transistor FET 116. 128P can be separated into multiple sections. One section can be closer to Source/drain region and other section can be closer to metal connection. Cheng does not teach the nanosheets, so nanosheet are combined from Lim reference.
Regarding claim 5, Cheng teaches (in view of Lim) the semiconductor structure of claim 4, wherein the metal connection is further electrically isolated from the first dummy gate by a plurality of inner spacers between the first set of nanosheets and by a sidewall spacer above the first set of nanosheets. Nanosheets are taught in Lim which are 18P in FIG. 1B. Nano sheets are adjacent to source/drain region of Active transistor FET 116. 128P can be separated into multiple sections. One section can be closer to Source/drain region and other section can be closer to metal connection. Cheng does not teach the nanosheets, so nanosheet are combined from Lim reference
Regarding claim 6, Cheng teaches (in view of Lim) the semiconductor structure of claim 5, wherein the metal connection (170 in FIG. 10A) includes a first portion between the first and the second dummy gate and between the first and the second set of sheets, and a second section that is surrounded by a backside interlevel dielectric layer underneath (205’, FIG. 11) the first and the second dummy transistor. Nanosheets are taught in Lim which are 18P in FIG. 1B. Nano sheets are adjacent to source/drain region of Active transistor FET 116. 128P can be separated into multiple sections. One section can be closer to Source/drain region and other section can be closer to metal connection. Cheng does not teach the nanosheets, so nanosheet are combined from Lim reference
Regarding claim 7, Cheng teaches (in view of Lim) the semiconductor structure of claim 2, wherein the first dummy transistor includes a first dummy gate (FIG. 11) that surrounds an end of a first set of sheets (these are dielectric layers), and the metal connection is separated from the end of the first set of sheets at least by the first dummy gate (120). gate layers 172 and 170 are formed on the strained fins 105′ between the spacer layers 125 in the area previously occupied by the cap and dummy gate layers 135 and 120. Nanosheets are taught in Lim which are 18P in FIG. 1B. Nano sheets are adjacent to source/drain region of Active transistor FET 116. 128P can be separated into multiple sections. One section can be closer to Source/drain region and other section can be closer to metal connection. Cheng does not teach the nanosheets, so nanosheet are combined from Lim reference
Regarding claim 8, Cheng teaches (in view of Lim) the semiconductor structure of claim 7, wherein the metal connection (170 in FIG. 10A) includes a first portion between the first and the second dummy transistor, and a second portion that is surrounded by a dummy diffusion break, and the dummy diffusion break is further surrounded by a backside interlevel dielectric layer (205’ in FIG. 11) underneath the first and the second dummy transistor (dummy transistor is shown in FIG. 11).
Regarding claim 17, Cheng teaches a semiconductor structure comprising:
an array of transistors on a semiconductor substrate, the array of transistors including a first dummy transistor; a second dummy transistor next to the first dummy transistor; a first active transistor next to the first dummy transistor opposite the second dummy transistor; and a second active transistor next to the second dummy transistor opposite the first dummy transistor (as per annotated FIG);
a connection between the first dummy transistor and the second dummy transistor (which include 260 and 255),
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wherein the connection connects a first contact at a frontside of the array of transistors to a second contact at a backside of the array of transistors (FIG. 10A or aa where frontside connect to backside of array transistor).
Cheng does not explicitly a metal connection between the first transistor and the second transistor.
However, Lim teaches metal connection between the first transistor and the second transistor wherein connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors (FIG. 1A, where 108A, 108B and metallization structure interconnect transistor different FETs.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Cheng’s transistor with teachings by Lim so that device power routing can be done efficiently without disturbing adjacent routing areas.
Regarding claim 18, Cheng teaches (in view of Lim) the semiconductor structure of claim 17, wherein the first dummy transistor includes a first dummy gate that surrounds a first set of nanosheets, the first set of nanosheets has a first section adjacent to the metal connection and a second section adjacent to a source/drain region of an active transistor, wherein the first section and the second section of the first set of nanosheets comprise different material. Nanosheets are taught in Lim which are 18P in FIG. 1B. Nano sheets are adjacent to source/drain region of Active transistor FET 116. 128P can be separated into multiple sections. One section can be closer to Source/drain region and other section can be closer to metal connection. Cheng does not teach the nanosheets, so nanosheet are combined from Lim reference.
Regarding claim 19, Cheng teaches (in view of Lim) the semiconductor structure of claim 18, wherein the metal connection (170 in FIG. 10A) includes a first portion between the first and the second dummy gate and between the first and the second set of sheets, and a second section that is surrounded by a backside interlevel dielectric layer underneath (205’, FIG. 11) the first and the second dummy transistor. Nanosheets are taught in Lim which are 18P in FIG. 1B. Nano sheets are adjacent to source/drain region of Active transistor FET 116. 128P can be separated into multiple sections. One section can be closer to Source/drain region and other section can be closer to metal connection. Cheng does not teach the nanosheets, so nanosheet are combined from Lim reference.
Regarding claim 20, Cheng teaches (in view of Lim) the semiconductor structure of claim 17, wherein the metal connection (170 in FIG. 10A) includes a first portion between the first and the second dummy transistor, and a second portion that is surrounded by a dummy diffusion break, and the dummy diffusion break is further surrounded by a backside interlevel dielectric layer (205’ in FIG. 11) underneath the first and the second dummy transistor (dummy transistor is shown in FIG. 11).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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